^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * pxa168 clock framework source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Chao Xie <xiechao.mail@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/clock/marvell,pxa168.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define APBC_RTC 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define APBC_TWSI0 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define APBC_KPC 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define APBC_UART0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define APBC_UART1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define APBC_GPIO 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define APBC_PWM0 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define APBC_PWM1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define APBC_PWM2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define APBC_PWM3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define APBC_TIMER 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define APBC_SSP0 0x81c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define APBC_SSP1 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define APBC_SSP2 0x84c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define APBC_SSP3 0x858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define APBC_SSP4 0x85c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define APBC_TWSI1 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define APBC_UART2 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define APMU_SDH0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define APMU_SDH1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define APMU_USB 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define APMU_DISP0 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define APMU_CCIC0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define APMU_DFC 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MPMU_UART_PLL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct pxa168_clk_unit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct mmp_clk_unit unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __iomem *mpmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void __iomem *apmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __iomem *apbc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {PXA168_CLK_CLK32, "clk32", NULL, 0, 32768},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {PXA168_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {PXA168_CLK_PLL1, "pll1", NULL, 0, 624000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {PXA168_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {PXA168_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct mmp_clk_factor_masks uart_factor_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .factor = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .num_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .den_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .num_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .den_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {.num = 8125, .den = 1536}, /*14.745MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct mmp_clk_unit *unit = &pxa_unit->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ARRAY_SIZE(fixed_rate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ARRAY_SIZE(fixed_factor_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk = mmp_clk_register_factor("uart_pll", "pll1_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pxa_unit->mpmu_base + MPMU_UART_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) &uart_factor_masks, uart_factor_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ARRAY_SIZE(uart_factor_tbl), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static DEFINE_SPINLOCK(uart0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static DEFINE_SPINLOCK(uart1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static DEFINE_SPINLOCK(uart2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static DEFINE_SPINLOCK(ssp0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static DEFINE_SPINLOCK(ssp1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static DEFINE_SPINLOCK(ssp2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static DEFINE_SPINLOCK(ssp3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static DEFINE_SPINLOCK(ssp4_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static DEFINE_SPINLOCK(timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const char *timer_parent_names[] = {"pll1_48", "clk32", "pll1_96", "pll1_192"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static DEFINE_SPINLOCK(reset_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct mmp_param_mux_clk apbc_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4, 3, 0, &ssp4_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER, 4, 3, 0, &timer_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct mmp_param_gate_clk apbc_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {PXA168_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {PXA168_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* The gate clocks has mux parent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {PXA168_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x3, 0x3, 0x0, 0, &ssp3_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {PXA168_CLK_SSP4, "ssp4_clk", "ssp4_mux", CLK_SET_RATE_PARENT, APBC_SSP4, 0x3, 0x3, 0x0, 0, &ssp4_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {PXA168_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x3, 0x3, 0x0, 0, &timer_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct mmp_clk_unit *unit = &pxa_unit->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ARRAY_SIZE(apbc_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ARRAY_SIZE(apbc_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static DEFINE_SPINLOCK(sdh0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static DEFINE_SPINLOCK(sdh1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static DEFINE_SPINLOCK(usb_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static DEFINE_SPINLOCK(disp0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static DEFINE_SPINLOCK(ccic0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct mmp_param_mux_clk apmu_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct mmp_param_div_clk apmu_div_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static struct mmp_param_gate_clk apmu_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {PXA168_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* The gate clocks has mux parent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void pxa168_axi_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct mmp_clk_unit *unit = &pxa_unit->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ARRAY_SIZE(apmu_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ARRAY_SIZE(apmu_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ARRAY_SIZE(apmu_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void pxa168_clk_reset_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct pxa168_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct mmp_clk_reset_cell *cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int i, nr_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) nr_resets = ARRAY_SIZE(apbc_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!cells)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) for (i = 0; i < nr_resets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cells[i].clk_id = apbc_gate_clks[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cells[i].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cells[i].lock = apbc_gate_clks[i].lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cells[i].bits = 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mmp_clk_reset_register(np, cells, nr_resets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void __init pxa168_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct pxa168_clk_unit *pxa_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pxa_unit->mpmu_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!pxa_unit->mpmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pr_err("failed to map mpmu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pxa_unit->apmu_base = of_iomap(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!pxa_unit->apmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pr_err("failed to map apmu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pxa_unit->apbc_base = of_iomap(np, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!pxa_unit->apbc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pr_err("failed to map apbc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pxa168_pll_init(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pxa168_apb_periph_clk_init(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pxa168_axi_periph_clk_init(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pxa168_clk_reset_init(np, pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CLK_OF_DECLARE(pxa168_clk, "marvell,pxa168-clock", pxa168_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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