^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * mmp2 clock framework source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Chao Xie <xiechao.mail@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <dt-bindings/clock/marvell,mmp2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <dt-bindings/power/marvell,mmp2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define APBC_RTC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define APBC_TWSI0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define APBC_TWSI1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define APBC_TWSI2 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define APBC_TWSI3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define APBC_TWSI4 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define APBC_TWSI5 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define APBC_KPC 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define APBC_TIMER 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define APBC_UART0 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define APBC_UART1 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define APBC_UART2 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define APBC_UART3 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define APBC_GPIO 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define APBC_PWM0 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define APBC_PWM1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define APBC_PWM2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define APBC_PWM3 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define APBC_SSP0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define APBC_SSP1 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define APBC_SSP2 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define APBC_SSP3 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define APBC_THERMAL0 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define APBC_THERMAL1 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define APBC_THERMAL2 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define APBC_THERMAL3 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define APMU_SDH0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define APMU_SDH1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define APMU_SDH2 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define APMU_SDH3 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define APMU_SDH4 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define APMU_USB 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define APMU_DISP0 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define APMU_DISP1 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define APMU_CCIC0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define APMU_CCIC1 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define APMU_USBHSIC0 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define APMU_USBHSIC1 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define APMU_GPU 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define APMU_AUDIO 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define APMU_CAMERA 0x1fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MPMU_FCCR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MPMU_POSR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MPMU_UART_PLL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MPMU_PLL2_CR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MPMU_I2S0_PLL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MPMU_I2S1_PLL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MPMU_ACGR 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* MMP3 specific below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MPMU_PLL3_CR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MPMU_PLL3_CTRL1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MPMU_PLL1_CTRL 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MPMU_PLL_DIFF_CTRL 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MPMU_PLL2_CTRL1 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum mmp2_clk_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CLK_MODEL_MMP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) CLK_MODEL_MMP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mmp2_clk_unit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mmp_clk_unit unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum mmp2_clk_model model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct genpd_onecell_data pd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct generic_pm_domain *pm_domains[MMP2_NR_POWER_DOMAINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void __iomem *mpmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __iomem *apmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *apbc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {MMP2_CLK_CLK32, "clk32", NULL, 0, 32768},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {0, "i2s_pll", NULL, 0, 99666667},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct mmp_param_pll_clk pll_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {MMP2_CLK_PLL1, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct mmp_param_pll_clk mmp3_pll_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {MMP2_CLK_PLL2, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0, 26000000, MPMU_PLL1_CTRL, 25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL2_CTRL1, 25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {MMP3_CLK_PLL1_P, "pll1_p", 0, MPMU_PLL_DIFF_CTRL, 0x0010, 0, 0, 797330000, MPMU_PLL_DIFF_CTRL, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {MMP3_CLK_PLL2_P, "pll2_p", 0, MPMU_PLL_DIFF_CTRL, 0x0100, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL_DIFF_CTRL, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {MMP3_CLK_PLL3, "pll3", 0, MPMU_PLL3_CR, 0x0300, MPMU_PLL3_CR, 10, 26000000, MPMU_PLL3_CTRL1, 25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct mmp_clk_factor_masks uart_factor_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .factor = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .num_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .den_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .num_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .den_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {.num = 8125, .den = 1536}, /*14.745MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {.num = 3521, .den = 689}, /*19.23MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct mmp_clk_factor_masks i2s_factor_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .factor = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .num_mask = 0x7fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .den_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .num_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .den_shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .enable_mask = 0xd0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct mmp_clk_factor_tbl i2s_factor_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {.num = 24868, .den = 511}, /* 2.0480 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {.num = 28003, .den = 793}, /* 2.8224 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {.num = 24941, .den = 1025}, /* 4.0960 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {.num = 28003, .den = 1586}, /* 5.6448 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {.num = 31158, .den = 2561}, /* 8.1920 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {.num = 16288, .den = 1845}, /* 11.2896 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {.num = 20772, .den = 2561}, /* 12.2880 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {.num = 8144, .den = 1845}, /* 22.5792 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {.num = 10386, .den = 2561}, /* 24.5760 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static DEFINE_SPINLOCK(acgr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct mmp_param_gate_clk mpmu_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0, &acgr_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0, &acgr_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void mmp2_main_clk_init(struct mmp2_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct mmp_clk_unit *unit = &pxa_unit->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ARRAY_SIZE(fixed_rate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (pxa_unit->model == CLK_MODEL_MMP3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mmp_register_pll_clks(unit, mmp3_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pxa_unit->mpmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ARRAY_SIZE(mmp3_pll_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mmp_register_pll_clks(unit, pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pxa_unit->mpmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ARRAY_SIZE(pll_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ARRAY_SIZE(fixed_factor_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk = mmp_clk_register_factor("uart_pll", "pll1_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pxa_unit->mpmu_base + MPMU_UART_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &uart_factor_masks, uart_factor_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ARRAY_SIZE(uart_factor_tbl), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mmp_clk_register_factor("i2s0_pll", "pll1_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pxa_unit->mpmu_base + MPMU_I2S0_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) &i2s_factor_masks, i2s_factor_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ARRAY_SIZE(i2s_factor_tbl), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mmp_clk_register_factor("i2s1_pll", "pll1_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pxa_unit->mpmu_base + MPMU_I2S1_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) &i2s_factor_masks, i2s_factor_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ARRAY_SIZE(i2s_factor_tbl), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mmp_register_gate_clks(unit, mpmu_gate_clks, pxa_unit->mpmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ARRAY_SIZE(mpmu_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static DEFINE_SPINLOCK(uart0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static DEFINE_SPINLOCK(uart1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static DEFINE_SPINLOCK(uart2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const char * const uart_parent_names[] = {"uart_pll", "vctcxo"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static DEFINE_SPINLOCK(ssp0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static DEFINE_SPINLOCK(ssp1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static DEFINE_SPINLOCK(ssp2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static DEFINE_SPINLOCK(ssp3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const char * const ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static DEFINE_SPINLOCK(timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const char * const timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static DEFINE_SPINLOCK(reset_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct mmp_param_mux_clk apbc_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER, 4, 3, 0, &timer_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct mmp_param_gate_clk apbc_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* The gate clocks has mux parent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {MMP2_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x7, 0x3, 0x0, 0, &timer_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {MMP2_CLK_THERMAL0, "thermal0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL0, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static struct mmp_param_gate_clk mmp3_apbc_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {MMP3_CLK_THERMAL1, "thermal1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL1, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {MMP3_CLK_THERMAL2, "thermal2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL2, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {MMP3_CLK_THERMAL3, "thermal3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL3, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct mmp_clk_unit *unit = &pxa_unit->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ARRAY_SIZE(apbc_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ARRAY_SIZE(apbc_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (pxa_unit->model == CLK_MODEL_MMP3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mmp_register_gate_clks(unit, mmp3_apbc_gate_clks, pxa_unit->apbc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ARRAY_SIZE(mmp3_apbc_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static DEFINE_SPINLOCK(sdh_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct mmp_clk_mix_config sdh_mix_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static DEFINE_SPINLOCK(usb_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static DEFINE_SPINLOCK(usbhsic0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static DEFINE_SPINLOCK(usbhsic1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static DEFINE_SPINLOCK(disp0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static DEFINE_SPINLOCK(disp1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static DEFINE_SPINLOCK(ccic0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static DEFINE_SPINLOCK(ccic1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const char * const ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static DEFINE_SPINLOCK(gpu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const char * const mmp2_gpu_gc_parent_names[] = {"pll1_2", "pll1_3", "pll2_2", "pll2_3", "pll2", "usb_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static u32 mmp2_gpu_gc_parent_table[] = { 0x0000, 0x0040, 0x0080, 0x00c0, 0x1000, 0x1040 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const char * const mmp2_gpu_bus_parent_names[] = {"pll1_4", "pll2", "pll2_2", "usb_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static u32 mmp2_gpu_bus_parent_table[] = { 0x0000, 0x0020, 0x0030, 0x4020 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const char * const mmp3_gpu_bus_parent_names[] = {"pll1_4", "pll1_6", "pll1_2", "pll2_2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const char * const mmp3_gpu_gc_parent_names[] = {"pll1", "pll2", "pll1_p", "pll2_p"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static DEFINE_SPINLOCK(audio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct mmp_clk_mix_config ccic0_mix_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct mmp_clk_mix_config ccic1_mix_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct mmp_param_mux_clk apmu_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct mmp_param_mux_clk mmp3_apmu_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0, "gpu_bus_mux", mmp3_gpu_bus_parent_names, ARRAY_SIZE(mmp3_gpu_bus_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CLK_SET_RATE_PARENT, APMU_GPU, 4, 2, 0, &gpu_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0, "gpu_3d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CLK_SET_RATE_PARENT, APMU_GPU, 6, 2, 0, &gpu_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0, "gpu_2d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) CLK_SET_RATE_PARENT, APMU_GPU, 12, 2, 0, &gpu_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct mmp_param_div_clk apmu_div_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct mmp_param_div_clk mmp3_apmu_div_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0, "gpu_3d_div", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 24, 4, 0, &gpu_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0, "gpu_2d_div", "gpu_2d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 28, 4, 0, &gpu_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct mmp_param_gate_clk apmu_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {MMP2_CLK_USBHSIC0, "usbhsic0_clk", "usb_pll", 0, APMU_USBHSIC0, 0x1b, 0x1b, 0x0, 0, &usbhsic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {MMP2_CLK_USBHSIC1, "usbhsic1_clk", "usb_pll", 0, APMU_USBHSIC1, 0x1b, 0x1b, 0x0, 0, &usbhsic1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* The gate clocks has mux parent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {MMP2_CLK_SDH2, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {MMP2_CLK_SDH3, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x12, 0x12, 0x0, 0, &disp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {MMP2_CLK_DISP0_LCDC, "disp0_lcdc_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x09, 0x09, 0x0, 0, &disp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x09, 0x09, 0x0, 0, &disp1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {MMP2_CLK_GPU_BUS, "gpu_bus_clk", "gpu_bus_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0xa, 0xa, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {MMP2_CLK_AUDIO, "audio_clk", "audio_mix_clk", CLK_SET_RATE_PARENT, APMU_AUDIO, 0x12, 0x12, 0x0, 0, &audio_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct mmp_param_gate_clk mmp2_apmu_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {MMP2_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static struct mmp_param_gate_clk mmp3_apmu_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {MMP3_CLK_SDH4, "sdh4_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH4, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {MMP3_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {MMP3_CLK_GPU_2D, "gpu_2d_clk", "gpu_2d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x1c0000, 0x1c0000, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct mmp_clk_unit *unit = &pxa_unit->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clk = mmp_clk_register_mix(NULL, "sdh_mix_clk", sdh_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ARRAY_SIZE(sdh_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) &sdh_mix_config, &sdh_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) clk = mmp_clk_register_mix(NULL, "ccic0_mix_clk", ccic_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ARRAY_SIZE(ccic_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &ccic0_mix_config, &ccic0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mmp_clk_add(unit, MMP2_CLK_CCIC0_MIX, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clk = mmp_clk_register_mix(NULL, "ccic1_mix_clk", ccic_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ARRAY_SIZE(ccic_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) &ccic1_mix_config, &ccic1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mmp_clk_add(unit, MMP2_CLK_CCIC1_MIX, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ARRAY_SIZE(apmu_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ARRAY_SIZE(apmu_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ARRAY_SIZE(apmu_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (pxa_unit->model == CLK_MODEL_MMP3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mmp_register_mux_clks(unit, mmp3_apmu_mux_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ARRAY_SIZE(mmp3_apmu_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mmp_register_div_clks(unit, mmp3_apmu_div_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ARRAY_SIZE(mmp3_apmu_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mmp_register_gate_clks(unit, mmp3_apmu_gate_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ARRAY_SIZE(mmp3_apmu_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) clk_register_mux_table(NULL, "gpu_3d_mux", mmp2_gpu_gc_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ARRAY_SIZE(mmp2_gpu_gc_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pxa_unit->apmu_base + APMU_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 0, 0x10c0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) mmp2_gpu_gc_parent_table, &gpu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clk_register_mux_table(NULL, "gpu_bus_mux", mmp2_gpu_bus_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ARRAY_SIZE(mmp2_gpu_bus_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) pxa_unit->apmu_base + APMU_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0, 0x4030, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mmp2_gpu_bus_parent_table, &gpu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mmp_register_gate_clks(unit, mmp2_apmu_gate_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ARRAY_SIZE(mmp2_apmu_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void mmp2_clk_reset_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct mmp2_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct mmp_clk_reset_cell *cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int i, nr_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) nr_resets = ARRAY_SIZE(apbc_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!cells)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) for (i = 0; i < nr_resets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) cells[i].clk_id = apbc_gate_clks[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) cells[i].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) cells[i].lock = apbc_gate_clks[i].lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) cells[i].bits = 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mmp_clk_reset_register(np, cells, nr_resets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void mmp2_pm_domain_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct mmp2_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (pxa_unit->model == CLK_MODEL_MMP3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) = mmp_pm_domain_register("gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pxa_unit->apmu_base + APMU_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 0x0600, 0x40003, 0x18000c, 0, &gpu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) = mmp_pm_domain_register("gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pxa_unit->apmu_base + APMU_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 0x8600, 0x00003, 0x00000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MMP_PM_DOMAIN_NO_DISABLE, &gpu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pxa_unit->pd_data.num_domains++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pxa_unit->pm_domains[MMP2_POWER_DOMAIN_AUDIO]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) = mmp_pm_domain_register("audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pxa_unit->apmu_base + APMU_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 0x600, 0x2, 0, 0, &audio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pxa_unit->pd_data.num_domains++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (pxa_unit->model == CLK_MODEL_MMP3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pxa_unit->pm_domains[MMP3_POWER_DOMAIN_CAMERA]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) = mmp_pm_domain_register("camera",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pxa_unit->apmu_base + APMU_CAMERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 0x600, 0, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pxa_unit->pd_data.num_domains++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pxa_unit->pd_data.domains = pxa_unit->pm_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) of_genpd_add_provider_onecell(np, &pxa_unit->pd_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void __init mmp2_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct mmp2_clk_unit *pxa_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (of_device_is_compatible(np, "marvell,mmp3-clock"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pxa_unit->model = CLK_MODEL_MMP3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pxa_unit->model = CLK_MODEL_MMP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pxa_unit->mpmu_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!pxa_unit->mpmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pr_err("failed to map mpmu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto free_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pxa_unit->apmu_base = of_iomap(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!pxa_unit->apmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pr_err("failed to map apmu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) goto unmap_mpmu_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pxa_unit->apbc_base = of_iomap(np, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!pxa_unit->apbc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pr_err("failed to map apbc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) goto unmap_apmu_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mmp2_pm_domain_init(np, pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mmp2_main_clk_init(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mmp2_apb_periph_clk_init(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mmp2_axi_periph_clk_init(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mmp2_clk_reset_init(np, pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unmap_apmu_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) iounmap(pxa_unit->apmu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unmap_mpmu_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) iounmap(pxa_unit->mpmu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) free_memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) kfree(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) CLK_OF_DECLARE(mmp3_clk, "marvell,mmp3-clock", mmp2_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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