^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * mmp2 clock framework source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Chao Xie <xiechao.mail@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk/mmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define APBC_RTC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define APBC_TWSI0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define APBC_TWSI1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define APBC_TWSI2 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define APBC_TWSI3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define APBC_TWSI4 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define APBC_TWSI5 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define APBC_KPC 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define APBC_UART0 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define APBC_UART1 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define APBC_UART2 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define APBC_UART3 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define APBC_GPIO 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define APBC_PWM0 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define APBC_PWM1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define APBC_PWM2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define APBC_PWM3 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define APBC_SSP0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define APBC_SSP1 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define APBC_SSP2 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define APBC_SSP3 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define APMU_SDH0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define APMU_SDH1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define APMU_SDH2 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define APMU_SDH3 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define APMU_USB 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define APMU_DISP0 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define APMU_DISP1 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define APMU_CCIC0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define APMU_CCIC1 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPMU_UART_PLL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static DEFINE_SPINLOCK(clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct mmp_clk_factor_masks uart_factor_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .factor = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .num_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .den_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .num_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .den_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {.num = 8125, .den = 1536}, /*14.745MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {.num = 3521, .den = 689}, /*19.23MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const char *uart_parent[] = {"uart_pll", "vctcxo"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) phys_addr_t apbc_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk *vctcxo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *mpmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __iomem *apmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *apbc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mpmu_base = ioremap(mpmu_phys, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!mpmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pr_err("error to ioremap MPMU base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) apmu_base = ioremap(apmu_phys, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (!apmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pr_err("error to ioremap APMU base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) apbc_base = ioremap(apbc_phys, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!apbc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pr_err("error to ioremap APBC base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk_register_clkdev(clk, "clk32", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk_register_clkdev(vctcxo, "vctcxo", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clk_register_clkdev(clk, "pll1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clk_register_clkdev(clk, "usb_pll", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clk_register_clkdev(clk, "pll2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clk_register_clkdev(clk, "pll1_2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clk_register_clkdev(clk, "pll1_4", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk_register_clkdev(clk, "pll1_8", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clk_register_clkdev(clk, "pll1_16", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CLK_SET_RATE_PARENT, 1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clk_register_clkdev(clk, "pll1_20", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CLK_SET_RATE_PARENT, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clk_register_clkdev(clk, "pll1_3", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) clk_register_clkdev(clk, "pll1_6", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clk_register_clkdev(clk, "pll1_12", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk_register_clkdev(clk, "pll2_2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) clk_register_clkdev(clk, "pll2_4", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk_register_clkdev(clk, "pll2_8", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk_register_clkdev(clk, "pll2_16", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CLK_SET_RATE_PARENT, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) clk_register_clkdev(clk, "pll2_3", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) clk_register_clkdev(clk, "pll2_6", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clk_register_clkdev(clk, "pll2_12", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) clk_register_clkdev(clk, "vctcxo_2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) clk_register_clkdev(clk, "vctcxo_4", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mpmu_base + MPMU_UART_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) &uart_factor_masks, uart_factor_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ARRAY_SIZE(uart_factor_tbl), &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) clk_set_rate(clk, 14745600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) clk_register_clkdev(clk, "uart_pll", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) clk = mmp_clk_register_apbc("twsi0", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clk = mmp_clk_register_apbc("twsi1", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk = mmp_clk_register_apbc("twsi2", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clk = mmp_clk_register_apbc("twsi3", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clk = mmp_clk_register_apbc("twsi4", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) clk = mmp_clk_register_apbc("twsi5", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk = mmp_clk_register_apbc("gpio", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) apbc_base + APBC_GPIO, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) clk_register_clkdev(clk, NULL, "mmp2-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) clk = mmp_clk_register_apbc("kpc", "clk32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) apbc_base + APBC_KPC, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clk_register_clkdev(clk, NULL, "pxa27x-keypad");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clk = mmp_clk_register_apbc("rtc", "clk32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) apbc_base + APBC_RTC, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clk_register_clkdev(clk, NULL, "mmp-rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) clk = mmp_clk_register_apbc("pwm0", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) apbc_base + APBC_PWM0, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clk = mmp_clk_register_apbc("pwm1", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) apbc_base + APBC_PWM1, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clk = mmp_clk_register_apbc("pwm2", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) apbc_base + APBC_PWM2, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) clk = mmp_clk_register_apbc("pwm3", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) apbc_base + APBC_PWM3, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ARRAY_SIZE(uart_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) clk_set_parent(clk, vctcxo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) clk_register_clkdev(clk, "uart_mux.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk = mmp_clk_register_apbc("uart0", "uart0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) apbc_base + APBC_UART0, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ARRAY_SIZE(uart_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clk_set_parent(clk, vctcxo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) clk_register_clkdev(clk, "uart_mux.1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clk = mmp_clk_register_apbc("uart1", "uart1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) apbc_base + APBC_UART1, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ARRAY_SIZE(uart_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) clk_set_parent(clk, vctcxo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk_register_clkdev(clk, "uart_mux.2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) clk = mmp_clk_register_apbc("uart2", "uart2_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) apbc_base + APBC_UART2, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ARRAY_SIZE(uart_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) clk_set_parent(clk, vctcxo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clk_register_clkdev(clk, "uart_mux.3", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clk = mmp_clk_register_apbc("uart3", "uart3_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) apbc_base + APBC_UART3, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ARRAY_SIZE(ssp_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) clk_register_clkdev(clk, "uart_mux.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) apbc_base + APBC_SSP0, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk_register_clkdev(clk, NULL, "mmp-ssp.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ARRAY_SIZE(ssp_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clk_register_clkdev(clk, "ssp_mux.1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) apbc_base + APBC_SSP1, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) clk_register_clkdev(clk, NULL, "mmp-ssp.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ARRAY_SIZE(ssp_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) clk_register_clkdev(clk, "ssp_mux.2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) apbc_base + APBC_SSP2, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) clk_register_clkdev(clk, NULL, "mmp-ssp.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ARRAY_SIZE(ssp_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) clk_register_clkdev(clk, "ssp_mux.3", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) apbc_base + APBC_SSP3, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) clk_register_clkdev(clk, NULL, "mmp-ssp.3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ARRAY_SIZE(sdh_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) clk_register_clkdev(clk, "sdh_mux", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) clk_register_clkdev(clk, "sdh_div", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x9, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clk_register_clkdev(clk, "usb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ARRAY_SIZE(disp_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) clk_register_clkdev(clk, "disp_mux.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) clk_register_clkdev(clk, "disp_div.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) clk = mmp_clk_register_apmu("disp0", "disp0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) apmu_base + APMU_DISP0, 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) clk_register_clkdev(clk, NULL, "mmp-disp.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) apmu_base + APMU_DISP0, 0x1024, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) clk_register_clkdev(clk, "disp_sphy.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ARRAY_SIZE(disp_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clk_register_clkdev(clk, "disp_mux.1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) clk_register_clkdev(clk, "disp_div.1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) clk = mmp_clk_register_apmu("disp1", "disp1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) apmu_base + APMU_DISP1, 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) clk_register_clkdev(clk, NULL, "mmp-disp.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) clk_register_clkdev(clk, "ccic_arbiter", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ARRAY_SIZE(ccic_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clk_register_clkdev(clk, "ccic_mux.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) clk_register_clkdev(clk, "ccic_div.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) apmu_base + APMU_CCIC0, 0x24, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 10, 5, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) apmu_base + APMU_CCIC0, 0x300, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ARRAY_SIZE(ccic_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) clk_register_clkdev(clk, "ccic_mux.1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) clk_register_clkdev(clk, "ccic_div.1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) apmu_base + APMU_CCIC1, 0x24, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 10, 5, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) apmu_base + APMU_CCIC1, 0x300, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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