^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * mmp gate clock operation source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Chao Xie <chao.xie@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Some clocks will have mutiple bits to enable the clocks, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * the bits to disable the clock is not same as enabling bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define to_clk_mmp_gate(hw) container_of(hw, struct mmp_clk_gate, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int mmp_clk_gate_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (gate->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) spin_lock_irqsave(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) tmp = readl(gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) tmp &= ~gate->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) tmp |= gate->val_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) writel(tmp, gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (gate->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) rate = clk_hw_get_rate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Need delay 2 cycles. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) udelay(2000000/rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void mmp_clk_gate_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (gate->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) spin_lock_irqsave(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) tmp = readl(gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) tmp &= ~gate->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) tmp |= gate->val_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel(tmp, gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (gate->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (gate->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) spin_lock_irqsave(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tmp = readl(gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (gate->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return (tmp & gate->mask) == gate->val_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct clk_ops mmp_clk_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .enable = mmp_clk_gate_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .disable = mmp_clk_gate_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .is_enabled = mmp_clk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int gate_flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mmp_clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* allocate the gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) init.ops = &mmp_clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* struct clk_gate assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) gate->mask = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) gate->val_enable = val_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) gate->val_disable = val_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) gate->flags = gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) gate->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clk = clk_register(dev, &gate->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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