Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * MMP Audio Clock Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/pm_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <dt-bindings/clock/marvell,mmp2-audio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* Audio Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SSPA_AUD_CTRL				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SSPA_AUD_PLL_CTRL0			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SSPA_AUD_PLL_CTRL1			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* SSPA Audio Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SSPA_AUD_CTRL_SYSCLK_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SSPA_AUD_CTRL_SYSCLK_DIV_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SSPA_AUD_CTRL_SSPA0_MUX_SHIFT		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SSPA_AUD_CTRL_SSPA0_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SSPA_AUD_CTRL_SSPA0_DIV_SHIFT		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SSPA_AUD_CTRL_SSPA1_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SSPA_AUD_CTRL_SSPA1_DIV_SHIFT		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SSPA_AUD_CTRL_SSPA1_MUX_SHIFT		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SSPA_AUD_CTRL_DIV_MASK			0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* SSPA Audio PLL Control 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO_MASK (0x7 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(x)	((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SSPA_AUD_PLL_CTRL0_FRACT_MASK		(0xfffff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SSPA_AUD_PLL_CTRL0_FRACT(x)		((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SSPA_AUD_PLL_CTRL0_ENA_DITHER		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SSPA_AUD_PLL_CTRL0_ICP_2UA		(0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SSPA_AUD_PLL_CTRL0_ICP_5UA		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SSPA_AUD_PLL_CTRL0_ICP_7UA		(2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SSPA_AUD_PLL_CTRL0_ICP_10UA		(3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SSPA_AUD_PLL_CTRL0_DIV_FBCCLK_MASK	(0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(x)	((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SSPA_AUD_PLL_CTRL0_DIV_MCLK_MASK	(0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SSPA_AUD_PLL_CTRL0_DIV_MCLK(x)		((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SSPA_AUD_PLL_CTRL0_PD_OVPROT_DIS	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SSPA_AUD_PLL_CTRL0_PU			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* SSPA Audio PLL Control 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SSPA_AUD_PLL_CTRL1_SEL_FAST_CLK		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SSPA_AUD_PLL_CTRL1_CLK_SEL_MASK		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL	(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SSPA_AUD_PLL_CTRL1_CLK_SEL_VCXO		(0 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK (0x7ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(x)	((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) struct mmp2_audio_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct clk_hw audio_pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct clk_mux sspa_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct clk_mux sspa1_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct clk_divider sysclk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct clk_divider sspa0_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct clk_divider sspa1_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct clk_gate sysclk_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct clk_gate sspa0_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct clk_gate sspa1_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 aud_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u32 aud_pll_ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u32 aud_pll_ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/* Must be last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct clk_hw_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	unsigned long freq_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	unsigned char mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned char fbcclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned short fract;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) } predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ 26000000, 135475200, 0, 0, 0x8a18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{ 26000000, 147456000, 0, 1, 0x0da1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{ 38400000, 135475200, 1, 2, 0x8208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{ 38400000, 147456000, 1, 3, 0xaaaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	unsigned char divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned char modulo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned char pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) } postdivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{   1,	3,  0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{   2,	5,  0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{   4,	0,  0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{   6,	1,  1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{   8,	1,  0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{   9,	1,  2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{  12,	2,  1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{  16,	2,  0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{  18,	2,  2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{  24,	4,  1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{  36,	4,  2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{  48,	6,  1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{  72,	6,  2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static unsigned long audio_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 					   unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct mmp2_audio_clk *priv = container_of(hw, struct mmp2_audio_clk, audio_pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned int prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned int postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u32 aud_pll_ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32 aud_pll_ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	aud_pll_ctrl0 &= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			 SSPA_AUD_PLL_CTRL0_FRACT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			 SSPA_AUD_PLL_CTRL0_ENA_DITHER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			 SSPA_AUD_PLL_CTRL0_DIV_FBCCLK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			 SSPA_AUD_PLL_CTRL0_DIV_MCLK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			 SSPA_AUD_PLL_CTRL0_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	aud_pll_ctrl1 &= SSPA_AUD_PLL_CTRL1_CLK_SEL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			 SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		if (predivs[prediv].parent_rate != parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			val = SSPA_AUD_PLL_CTRL0_ENA_DITHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			val |= SSPA_AUD_PLL_CTRL0_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			if (val != aud_pll_ctrl0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			val = SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			if (val != aud_pll_ctrl1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			freq = predivs[prediv].freq_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			freq /= postdivs[postdiv].divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static long audio_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				 unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned int prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	unsigned int postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	long rounded = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		if (predivs[prediv].parent_rate != *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			long freq = predivs[prediv].freq_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			freq /= postdivs[postdiv].divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			if (freq == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			if (freq < rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			if (rounded && freq > rounded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			rounded = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return rounded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int audio_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			      unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct mmp2_audio_clk *priv = container_of(hw, struct mmp2_audio_clk, audio_pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	unsigned int prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	unsigned int postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		if (predivs[prediv].parent_rate != parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			if (rate * postdivs[postdiv].divisor != predivs[prediv].freq_vco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			val = SSPA_AUD_PLL_CTRL0_ENA_DITHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			val |= SSPA_AUD_PLL_CTRL0_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			val = SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct clk_ops audio_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.recalc_rate = audio_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.round_rate = audio_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.set_rate = audio_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int register_clocks(struct mmp2_audio_clk *priv, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	const struct clk_parent_data sspa_mux_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		{ .hw = &priv->audio_pll_hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		{ .fw_name = "i2s0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	const struct clk_parent_data sspa1_mux_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		{ .hw = &priv->audio_pll_hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		{ .fw_name = "i2s1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	priv->audio_pll_hw.init = CLK_HW_INIT_FW_NAME("audio_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				"vctcxo", &audio_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ret = devm_clk_hw_register(dev, &priv->audio_pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	priv->sspa_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				sspa_mux_parents, &clk_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	priv->sspa_mux.mask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	priv->sspa_mux.shift = SSPA_AUD_CTRL_SSPA0_MUX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = devm_clk_hw_register(dev, &priv->sspa_mux.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	priv->sysclk_div.hw.init = CLK_HW_INIT_HW("sys_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				&priv->sspa_mux.hw, &clk_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	priv->sysclk_div.shift = SSPA_AUD_CTRL_SYSCLK_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	priv->sysclk_div.width = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	priv->sysclk_div.flags = CLK_DIVIDER_ONE_BASED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	priv->sysclk_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	priv->sysclk_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ret = devm_clk_hw_register(dev, &priv->sysclk_div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	priv->sysclk_gate.hw.init = CLK_HW_INIT_HW("sys_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				&priv->sysclk_div.hw, &clk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	priv->sysclk_gate.bit_idx = SSPA_AUD_CTRL_SYSCLK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	ret = devm_clk_hw_register(dev, &priv->sysclk_gate.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	priv->sspa0_div.hw.init = CLK_HW_INIT_HW("sspa0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 				&priv->sspa_mux.hw, &clk_divider_ops, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	priv->sspa0_div.shift = SSPA_AUD_CTRL_SSPA0_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	priv->sspa0_div.width = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	priv->sspa0_div.flags = CLK_DIVIDER_ONE_BASED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	priv->sspa0_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	priv->sspa0_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	ret = devm_clk_hw_register(dev, &priv->sspa0_div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	priv->sspa0_gate.hw.init = CLK_HW_INIT_HW("sspa0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				&priv->sspa0_div.hw, &clk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	priv->sspa0_gate.bit_idx = SSPA_AUD_CTRL_SSPA0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	ret = devm_clk_hw_register(dev, &priv->sspa0_gate.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	priv->sspa1_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 				sspa1_mux_parents, &clk_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 				CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	priv->sspa1_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	priv->sspa1_mux.mask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	priv->sspa1_mux.shift = SSPA_AUD_CTRL_SSPA1_MUX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	ret = devm_clk_hw_register(dev, &priv->sspa1_mux.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	priv->sspa1_div.hw.init = CLK_HW_INIT_HW("sspa1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				&priv->sspa1_mux.hw, &clk_divider_ops, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	priv->sspa1_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	priv->sspa1_div.shift = SSPA_AUD_CTRL_SSPA1_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	priv->sspa1_div.width = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	priv->sspa1_div.flags = CLK_DIVIDER_ONE_BASED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	priv->sspa1_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	priv->sspa1_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	ret = devm_clk_hw_register(dev, &priv->sspa1_div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	priv->sspa1_gate.hw.init = CLK_HW_INIT_HW("sspa1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 				&priv->sspa1_div.hw, &clk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 				CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	priv->sspa1_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	priv->sspa1_gate.bit_idx = SSPA_AUD_CTRL_SSPA1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	ret = devm_clk_hw_register(dev, &priv->sspa1_gate.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	priv->clk_data.hws[MMP2_CLK_AUDIO_SYSCLK] = &priv->sysclk_gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA0] = &priv->sspa0_gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA1] = &priv->sspa1_gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	priv->clk_data.num = MMP2_CLK_AUDIO_NR_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 				      &priv->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int mmp2_audio_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct mmp2_audio_clk *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	priv = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			    struct_size(priv, clk_data.hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 					MMP2_CLK_AUDIO_NR_CLKS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	priv->mmio_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (IS_ERR(priv->mmio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		return PTR_ERR(priv->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	ret = pm_clk_create(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		goto disable_pm_runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	ret = pm_clk_add(&pdev->dev, "audio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		goto destroy_pm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	ret = register_clocks(priv, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		goto destroy_pm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) destroy_pm_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	pm_clk_destroy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) disable_pm_runtime:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int mmp2_audio_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	pm_clk_destroy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int mmp2_audio_clk_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	struct mmp2_audio_clk *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	priv->aud_ctrl = readl(priv->mmio_base + SSPA_AUD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	priv->aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	priv->aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	pm_clk_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int mmp2_audio_clk_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	struct mmp2_audio_clk *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	pm_clk_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	writel(priv->aud_ctrl, priv->mmio_base + SSPA_AUD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	writel(priv->aud_pll_ctrl0, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	writel(priv->aud_pll_ctrl1, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const struct dev_pm_ops mmp2_audio_clk_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	SET_RUNTIME_PM_OPS(mmp2_audio_clk_suspend, mmp2_audio_clk_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct of_device_id mmp2_audio_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	{ .compatible = "marvell,mmp2-audio-clock" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MODULE_DEVICE_TABLE(of, mmp2_audio_clk_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct platform_driver mmp2_audio_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		.name = "mmp2-audio-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		.of_match_table = of_match_ptr(mmp2_audio_clk_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		.pm = &mmp2_audio_clk_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.probe = mmp2_audio_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.remove = mmp2_audio_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) module_platform_driver(mmp2_audio_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_DESCRIPTION("Clock driver for MMP2 Audio subsystem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_LICENSE("GPL");