Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * mmp AXI peripharal clock operation source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Chao Xie <xiechao.mail@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk_apmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	struct clk_hw   hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	void __iomem    *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	u32		rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	u32		enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	spinlock_t	*lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int clk_apmu_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct clk_apmu *apmu = to_clk_apmu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	if (apmu->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		spin_lock_irqsave(apmu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	data = readl_relaxed(apmu->base) | apmu->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	writel_relaxed(data, apmu->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	if (apmu->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		spin_unlock_irqrestore(apmu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void clk_apmu_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	struct clk_apmu *apmu = to_clk_apmu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	if (apmu->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		spin_lock_irqsave(apmu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	writel_relaxed(data, apmu->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	if (apmu->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		spin_unlock_irqrestore(apmu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct clk_ops clk_apmu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	.enable = clk_apmu_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	.disable = clk_apmu_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		void __iomem *base, u32 enable_mask, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	struct clk_apmu *apmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	apmu = kzalloc(sizeof(*apmu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	if (!apmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	init.ops = &clk_apmu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	apmu->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	apmu->enable_mask = enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	apmu->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	apmu->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	clk = clk_register(NULL, &apmu->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 		kfree(apmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }