^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * mmp APB clock operation source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Chao Xie <xiechao.mail@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Common APB clock register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define APBC_RST (1 << 2) /* Reset Generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define APBC_POWER (1 << 7) /* Reset Generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define to_clk_apbc(hw) container_of(hw, struct clk_apbc, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_apbc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int clk_apbc_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk_apbc *apbc = to_clk_apbc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * It may share same register as MUX clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * and it will impact FNCLK enable. Spinlock is needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (apbc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) spin_lock_irqsave(apbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) data = readl_relaxed(apbc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (apbc->flags & APBC_POWER_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) data |= APBC_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) data |= APBC_FNCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) writel_relaxed(data, apbc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (apbc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) spin_unlock_irqrestore(apbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) udelay(apbc->delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (apbc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) spin_lock_irqsave(apbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) data = readl_relaxed(apbc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) data |= APBC_APBCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel_relaxed(data, apbc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (apbc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) spin_unlock_irqrestore(apbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) udelay(apbc->delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!(apbc->flags & APBC_NO_BUS_CTRL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (apbc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) spin_lock_irqsave(apbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) data = readl_relaxed(apbc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) data &= ~APBC_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writel_relaxed(data, apbc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (apbc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) spin_unlock_irqrestore(apbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void clk_apbc_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk_apbc *apbc = to_clk_apbc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (apbc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spin_lock_irqsave(apbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) data = readl_relaxed(apbc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (apbc->flags & APBC_POWER_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) data &= ~APBC_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) data &= ~APBC_FNCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel_relaxed(data, apbc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (apbc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) spin_unlock_irqrestore(apbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (apbc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) spin_lock_irqsave(apbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) data = readl_relaxed(apbc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) data &= ~APBC_APBCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writel_relaxed(data, apbc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (apbc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) spin_unlock_irqrestore(apbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct clk_ops clk_apbc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .prepare = clk_apbc_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .unprepare = clk_apbc_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void __iomem *base, unsigned int delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int apbc_flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk_apbc *apbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) apbc = kzalloc(sizeof(*apbc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!apbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) init.ops = &clk_apbc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) apbc->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) apbc->delay = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) apbc->flags = apbc_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) apbc->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) apbc->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clk = clk_register(NULL, &apbc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) kfree(apbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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