^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "vid-pll-div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static inline struct meson_vid_pll_div_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) meson_vid_pll_div_data(struct clk_regmap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) return (struct meson_vid_pll_div_data *)clk->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * This vid_pll divided is a fully programmable fractionnal divider to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * achieve complex video clock rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Here are provided the commonly used fraction values provided by Amlogic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct vid_pll_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int shift_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int shift_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VID_PLL_DIV(_val, _sel, _ft, _fb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .shift_val = (_val), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .shift_sel = (_sel), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .divider = (_ft), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .multiplier = (_fb), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct vid_pll_div vid_pll_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) VID_PLL_DIV(0x0aaa, 0, 2, 1), /* 2/1 => /2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) VID_PLL_DIV(0x5294, 2, 5, 2), /* 5/2 => /2.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) VID_PLL_DIV(0x0db6, 0, 3, 1), /* 3/1 => /3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) VID_PLL_DIV(0x36cc, 1, 7, 2), /* 7/2 => /3.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) VID_PLL_DIV(0x6666, 2, 15, 4), /* 15/4 => /3.75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) VID_PLL_DIV(0x0ccc, 0, 4, 1), /* 4/1 => /4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) VID_PLL_DIV(0x739c, 2, 5, 1), /* 5/1 => /5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) VID_PLL_DIV(0x0e38, 0, 6, 1), /* 6/1 => /6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) VID_PLL_DIV(0x0000, 3, 25, 4), /* 25/4 => /6.25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) VID_PLL_DIV(0x3c78, 1, 7, 1), /* 7/1 => /7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) VID_PLL_DIV(0x78f0, 2, 15, 2), /* 15/2 => /7.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) VID_PLL_DIV(0x0fc0, 0, 12, 1), /* 12/1 => /12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) VID_PLL_DIV(0x3f80, 1, 14, 1), /* 14/1 => /14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) VID_PLL_DIV(0x7f80, 2, 15, 1), /* 15/1 => /15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define to_meson_vid_pll_div(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) container_of(_hw, struct meson_vid_pll_div, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct vid_pll_div *_get_table_val(unsigned int shift_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int shift_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for (i = 0 ; i < ARRAY_SIZE(vid_pll_div_table) ; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (vid_pll_div_table[i].shift_val == shift_val &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) vid_pll_div_table[i].shift_sel == shift_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return &vid_pll_div_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const struct vid_pll_div *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) div = _get_table_val(meson_parm_read(clk->map, &pll_div->val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) meson_parm_read(clk->map, &pll_div->sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!div || !div->divider) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pr_debug("%s: Invalid config value for vid_pll_div\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct clk_ops meson_vid_pll_div_ro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .recalc_rate = meson_vid_pll_div_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) EXPORT_SYMBOL_GPL(meson_vid_pll_div_ro_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MODULE_DESCRIPTION("Amlogic video pll divider driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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