^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 Endless Mobile, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Carlo Caione <carlo@endlessm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2016 BayLibre, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Michael Turquette <mturquette@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "meson8b.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-mpll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static DEFINE_SPINLOCK(meson_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct meson8b_clk_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct reset_controller_dev reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const struct pll_params_table sys_pll_params_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PLL_PARAMS(50, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PLL_PARAMS(51, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PLL_PARAMS(52, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PLL_PARAMS(53, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PLL_PARAMS(54, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PLL_PARAMS(55, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PLL_PARAMS(56, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PLL_PARAMS(57, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PLL_PARAMS(58, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PLL_PARAMS(59, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PLL_PARAMS(60, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PLL_PARAMS(61, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PLL_PARAMS(62, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PLL_PARAMS(63, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PLL_PARAMS(64, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PLL_PARAMS(65, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PLL_PARAMS(66, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PLL_PARAMS(67, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PLL_PARAMS(68, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PLL_PARAMS(84, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct clk_fixed_rate meson8b_xtal = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .fixed_rate = 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .num_parents = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .ops = &clk_fixed_rate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct clk_regmap meson8b_fixed_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .reg_off = HHI_MPLL_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "fixed_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct clk_regmap meson8b_fixed_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .offset = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "fixed_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) &meson8b_fixed_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * This clock won't ever change at runtime so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * CLK_SET_RATE_PARENT is not required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct clk_regmap meson8b_hdmi_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .reg_off = HHI_VID_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .reg_off = HHI_VID_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .reg_off = HHI_VID_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .reg_off = HHI_VID_PLL_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .reg_off = HHI_VID_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .reg_off = HHI_VID_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* sometimes also called "HPLL" or "HPLL PLL" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "hdmi_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .offset = HHI_VID_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "hdmi_pll_lvds_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) &meson8b_hdmi_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .offset = HHI_VID_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "hdmi_pll_hdmi_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) &meson8b_hdmi_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct clk_regmap meson8b_sys_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .table = sys_pll_params_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "sys_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct clk_regmap meson8b_sys_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .offset = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = "sys_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) &meson8b_sys_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct clk_fixed_factor meson8b_fclk_div2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "fclk_div2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) &meson8b_fixed_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct clk_regmap meson8b_fclk_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .bit_idx = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "fclk_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) &meson8b_fclk_div2_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct clk_fixed_factor meson8b_fclk_div3_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .div = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .name = "fclk_div3_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) &meson8b_fixed_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct clk_regmap meson8b_fclk_div3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .bit_idx = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .name = "fclk_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) &meson8b_fclk_div3_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct clk_fixed_factor meson8b_fclk_div4_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .name = "fclk_div4_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) &meson8b_fixed_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct clk_regmap meson8b_fclk_div4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .bit_idx = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .name = "fclk_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &meson8b_fclk_div4_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct clk_fixed_factor meson8b_fclk_div5_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .div = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .name = "fclk_div5_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) &meson8b_fixed_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static struct clk_regmap meson8b_fclk_div5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .bit_idx = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .name = "fclk_div5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) &meson8b_fclk_div5_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct clk_fixed_factor meson8b_fclk_div7_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .div = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .name = "fclk_div7_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) &meson8b_fixed_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct clk_regmap meson8b_fclk_div7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .bit_idx = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "fclk_div7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) &meson8b_fclk_div7_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct clk_regmap meson8b_mpll_prediv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .offset = HHI_MPLL_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "mpll_prediv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) &meson8b_fixed_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static struct clk_regmap meson8b_mpll0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .ssen = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .name = "mpll0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &meson8b_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct clk_regmap meson8b_mpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .offset = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .bit_idx = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .name = "mpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) &meson8b_mpll0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static struct clk_regmap meson8b_mpll1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .reg_off = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .reg_off = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .reg_off = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .name = "mpll1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &meson8b_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct clk_regmap meson8b_mpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .offset = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .bit_idx = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .name = "mpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &meson8b_mpll1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static struct clk_regmap meson8b_mpll2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .reg_off = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .reg_off = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .reg_off = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .name = "mpll2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) &meson8b_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static struct clk_regmap meson8b_mpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .offset = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .bit_idx = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .name = "mpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) &meson8b_mpll2_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static u32 mux_table_clk81[] = { 6, 5, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static struct clk_regmap meson8b_mpeg_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .table = mux_table_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .name = "mpeg_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * FIXME bits 14:12 selects from 8 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * fclk_div4, fclk_div3, fclk_div5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) &meson8b_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) &meson8b_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) &meson8b_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static struct clk_regmap meson8b_mpeg_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .name = "mpeg_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) &meson8b_mpeg_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct clk_regmap meson8b_clk81 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .name = "clk81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) &meson8b_mpeg_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static struct clk_regmap meson8b_cpu_in_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .name = "cpu_in_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .parent_data = (const struct clk_parent_data[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { .fw_name = "xtal", .name = "xtal", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { .hw = &meson8b_sys_pll.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .flags = (CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) CLK_SET_RATE_NO_REPARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static struct clk_fixed_factor meson8b_cpu_in_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .name = "cpu_in_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) &meson8b_cpu_in_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static struct clk_fixed_factor meson8b_cpu_in_div3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .div = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .name = "cpu_in_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) &meson8b_cpu_in_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static const struct clk_div_table cpu_scale_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { .val = 1, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { .val = 2, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { .val = 4, .div = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { .val = 5, .div = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { .val = 6, .div = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { .val = 7, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { .val = 8, .div = 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static struct clk_regmap meson8b_cpu_scale_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .width = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .table = cpu_scale_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .flags = CLK_DIVIDER_ALLOW_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .name = "cpu_scale_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) &meson8b_cpu_in_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct clk_regmap meson8b_cpu_scale_out_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .table = mux_table_cpu_scale_out_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .name = "cpu_scale_out_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * NOTE: We are skipping the parent with value 0x2 (which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * meson8b_cpu_in_div3) because it results in a duty cycle of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * 33% which makes the system unstable and can result in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * lockup of the whole system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) &meson8b_cpu_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) &meson8b_cpu_in_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &meson8b_cpu_scale_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static struct clk_regmap meson8b_cpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .shift = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .name = "cpu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .parent_data = (const struct clk_parent_data[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) { .fw_name = "xtal", .name = "xtal", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) { .hw = &meson8b_cpu_scale_out_sel.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .flags = (CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) CLK_SET_RATE_NO_REPARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static struct clk_regmap meson8b_nand_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .name = "nand_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* FIXME all other parents are unknown: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .parent_data = (const struct clk_parent_data[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) { .hw = &meson8b_fclk_div4.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) { .hw = &meson8b_fclk_div3.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { .hw = &meson8b_fclk_div5.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) { .hw = &meson8b_fclk_div7.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) { .fw_name = "xtal", .name = "xtal", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static struct clk_regmap meson8b_nand_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .name = "nand_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) &meson8b_nand_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static struct clk_regmap meson8b_nand_clk_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .name = "nand_clk_gate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) &meson8b_nand_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .name = "cpu_clk_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) &meson8b_cpu_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .div = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .name = "cpu_clk_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) &meson8b_cpu_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .name = "cpu_clk_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) &meson8b_cpu_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .div = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .name = "cpu_clk_div5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) &meson8b_cpu_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .div = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .name = "cpu_clk_div6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &meson8b_cpu_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .div = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .name = "cpu_clk_div7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) &meson8b_cpu_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .div = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .name = "cpu_clk_div8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) &meson8b_cpu_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static struct clk_regmap meson8b_apb_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .table = mux_table_apb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .name = "apb_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) &meson8b_cpu_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) &meson8b_cpu_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) &meson8b_cpu_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) &meson8b_cpu_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) &meson8b_cpu_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &meson8b_cpu_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) &meson8b_cpu_clk_div8.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static struct clk_regmap meson8b_apb_clk_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .bit_idx = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .flags = CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .name = "apb_clk_dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) &meson8b_apb_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static struct clk_regmap meson8b_periph_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .name = "periph_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) &meson8b_cpu_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) &meson8b_cpu_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) &meson8b_cpu_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) &meson8b_cpu_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) &meson8b_cpu_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) &meson8b_cpu_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) &meson8b_cpu_clk_div8.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static struct clk_regmap meson8b_periph_clk_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .bit_idx = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .flags = CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .name = "periph_clk_dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) &meson8b_periph_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static struct clk_regmap meson8b_axi_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .table = mux_table_axi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .name = "axi_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) &meson8b_cpu_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) &meson8b_cpu_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) &meson8b_cpu_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) &meson8b_cpu_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) &meson8b_cpu_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) &meson8b_cpu_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) &meson8b_cpu_clk_div8.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static struct clk_regmap meson8b_axi_clk_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .bit_idx = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .flags = CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .name = "axi_clk_dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) &meson8b_axi_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static struct clk_regmap meson8b_l2_dram_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .name = "l2_dram_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) &meson8b_cpu_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) &meson8b_cpu_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) &meson8b_cpu_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) &meson8b_cpu_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) &meson8b_cpu_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) &meson8b_cpu_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) &meson8b_cpu_clk_div8.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static struct clk_regmap meson8b_l2_dram_clk_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .bit_idx = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .flags = CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .name = "l2_dram_clk_dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) &meson8b_l2_dram_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static struct clk_regmap meson8b_vid_pll_in_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .offset = HHI_VID_DIVIDER_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .name = "vid_pll_in_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * TODO: depending on the SoC there is also a second parent:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * Meson8: unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * Meson8b: hdmi_pll_dco
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * Meson8m2: vid2_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) &meson8b_hdmi_pll_lvds_out.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static struct clk_regmap meson8b_vid_pll_in_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .offset = HHI_VID_DIVIDER_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .bit_idx = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .name = "vid_pll_in_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) &meson8b_vid_pll_in_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static struct clk_regmap meson8b_vid_pll_pre_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .offset = HHI_VID_DIVIDER_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .name = "vid_pll_pre_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) &meson8b_vid_pll_in_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static struct clk_regmap meson8b_vid_pll_post_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .offset = HHI_VID_DIVIDER_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .name = "vid_pll_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) &meson8b_vid_pll_pre_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static struct clk_regmap meson8b_vid_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .offset = HHI_VID_DIVIDER_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .name = "vid_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) &meson8b_vid_pll_pre_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) &meson8b_vid_pll_post_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static struct clk_regmap meson8b_vid_pll_final_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .name = "vid_pll_final_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) &meson8b_vid_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) &meson8b_vid_pll_final_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) &meson8b_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) &meson8b_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) &meson8b_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) &meson8b_vid_pll_final_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) &meson8b_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) &meson8b_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static struct clk_regmap meson8b_vclk_in_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .name = "vclk_in_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .parent_hws = meson8b_vclk_mux_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static struct clk_regmap meson8b_vclk_in_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .bit_idx = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .name = "vclk_in_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) &meson8b_vclk_in_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static struct clk_regmap meson8b_vclk_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .bit_idx = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .name = "vclk_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) &meson8b_vclk_in_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static struct clk_regmap meson8b_vclk_div1_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .name = "vclk_div1_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) &meson8b_vclk_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static struct clk_fixed_factor meson8b_vclk_div2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .name = "vclk_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) &meson8b_vclk_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static struct clk_regmap meson8b_vclk_div2_div_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .name = "vclk_div2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) &meson8b_vclk_div2_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static struct clk_fixed_factor meson8b_vclk_div4_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .name = "vclk_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) &meson8b_vclk_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static struct clk_regmap meson8b_vclk_div4_div_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .bit_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .name = "vclk_div4_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) &meson8b_vclk_div4_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static struct clk_fixed_factor meson8b_vclk_div6_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .div = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .name = "vclk_div6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) &meson8b_vclk_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static struct clk_regmap meson8b_vclk_div6_div_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .bit_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .name = "vclk_div6_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) &meson8b_vclk_div6_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static struct clk_fixed_factor meson8b_vclk_div12_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .div = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .name = "vclk_div12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) &meson8b_vclk_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static struct clk_regmap meson8b_vclk_div12_div_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .bit_idx = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .name = "vclk_div12_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) &meson8b_vclk_div12_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static struct clk_regmap meson8b_vclk2_in_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .name = "vclk2_in_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .parent_hws = meson8b_vclk_mux_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static struct clk_regmap meson8b_vclk2_clk_in_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .bit_idx = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .name = "vclk2_in_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) &meson8b_vclk2_in_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static struct clk_regmap meson8b_vclk2_clk_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .bit_idx = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .name = "vclk2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) &meson8b_vclk2_clk_in_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static struct clk_regmap meson8b_vclk2_div1_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .name = "vclk2_div1_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) &meson8b_vclk2_clk_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static struct clk_fixed_factor meson8b_vclk2_div2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .name = "vclk2_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) &meson8b_vclk2_clk_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static struct clk_regmap meson8b_vclk2_div2_div_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .name = "vclk2_div2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) &meson8b_vclk2_div2_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static struct clk_fixed_factor meson8b_vclk2_div4_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .name = "vclk2_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) &meson8b_vclk2_clk_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static struct clk_regmap meson8b_vclk2_div4_div_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .bit_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .name = "vclk2_div4_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) &meson8b_vclk2_div4_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static struct clk_fixed_factor meson8b_vclk2_div6_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .div = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .name = "vclk2_div6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) &meson8b_vclk2_clk_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static struct clk_regmap meson8b_vclk2_div6_div_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .bit_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .name = "vclk2_div6_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) &meson8b_vclk2_div6_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static struct clk_fixed_factor meson8b_vclk2_div12_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .div = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .name = "vclk2_div12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) &meson8b_vclk2_clk_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static struct clk_regmap meson8b_vclk2_div12_div_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .bit_idx = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .name = "vclk2_div12_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) &meson8b_vclk2_div12_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) &meson8b_vclk_div1_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) &meson8b_vclk_div2_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) &meson8b_vclk_div4_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) &meson8b_vclk_div6_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) &meson8b_vclk_div12_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static struct clk_regmap meson8b_cts_enct_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .name = "cts_enct_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .parent_hws = meson8b_vclk_enc_mux_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static struct clk_regmap meson8b_cts_enct = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .name = "cts_enct",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) &meson8b_cts_enct_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static struct clk_regmap meson8b_cts_encp_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .name = "cts_encp_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .parent_hws = meson8b_vclk_enc_mux_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static struct clk_regmap meson8b_cts_encp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .bit_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .name = "cts_encp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) &meson8b_cts_encp_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static struct clk_regmap meson8b_cts_enci_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .name = "cts_enci_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .parent_hws = meson8b_vclk_enc_mux_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static struct clk_regmap meson8b_cts_enci = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .name = "cts_enci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) &meson8b_cts_enci_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .name = "hdmi_tx_pixel_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .parent_hws = meson8b_vclk_enc_mux_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static struct clk_regmap meson8b_hdmi_tx_pixel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .bit_idx = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .name = "hdmi_tx_pixel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) &meson8b_hdmi_tx_pixel_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) &meson8b_vclk2_div1_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) &meson8b_vclk2_div2_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) &meson8b_vclk2_div4_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) &meson8b_vclk2_div6_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) &meson8b_vclk2_div12_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) static struct clk_regmap meson8b_cts_encl_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .name = "cts_encl_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static struct clk_regmap meson8b_cts_encl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .bit_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .name = "cts_encl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) &meson8b_cts_encl_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static struct clk_regmap meson8b_cts_vdac0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .name = "cts_vdac0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static struct clk_regmap meson8b_cts_vdac0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .bit_idx = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .name = "cts_vdac0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) &meson8b_cts_vdac0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static struct clk_regmap meson8b_hdmi_sys_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .name = "hdmi_sys_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /* FIXME: all other parents are unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static struct clk_regmap meson8b_hdmi_sys_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .name = "hdmi_sys_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) &meson8b_hdmi_sys_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) static struct clk_regmap meson8b_hdmi_sys = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .name = "hdmi_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) &meson8b_hdmi_sys_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) * actually manage this glitch-free mux because it does top-to-bottom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) * updates the each clock tree and switches to the "inactive" one when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) * CLK_SET_RATE_GATE is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) * Meson8 only has mali_0 and no glitch-free mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) { .fw_name = "xtal", .name = "xtal", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) { .hw = &meson8b_mpll2.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) { .hw = &meson8b_mpll1.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) { .hw = &meson8b_fclk_div7.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) { .hw = &meson8b_fclk_div4.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) { .hw = &meson8b_fclk_div3.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) { .hw = &meson8b_fclk_div5.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static struct clk_regmap meson8b_mali_0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .table = meson8b_mali_0_1_mux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .name = "mali_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .parent_data = meson8b_mali_0_1_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) * Don't propagate rate changes up because the only changeable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) * parents are mpll1 and mpll2 but we need those for audio and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) * RGMII (Ethernet). We don't want to change the audio or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) * Ethernet clocks when setting the GPU frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static struct clk_regmap meson8b_mali_0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .name = "mali_0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) &meson8b_mali_0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static struct clk_regmap meson8b_mali_0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .name = "mali_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) &meson8b_mali_0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static struct clk_regmap meson8b_mali_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .table = meson8b_mali_0_1_mux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .name = "mali_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .parent_data = meson8b_mali_0_1_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) * Don't propagate rate changes up because the only changeable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) * parents are mpll1 and mpll2 but we need those for audio and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) * RGMII (Ethernet). We don't want to change the audio or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) * Ethernet clocks when setting the GPU frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) static struct clk_regmap meson8b_mali_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .name = "mali_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) &meson8b_mali_1_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static struct clk_regmap meson8b_mali_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .name = "mali_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) &meson8b_mali_1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) static struct clk_regmap meson8b_mali = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .name = "mali",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) &meson8b_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) &meson8b_mali_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static const struct reg_sequence meson8m2_gp_pll_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) { .reg = HHI_GP_PLL_CNTL2, .def = 0x59c88000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) { .reg = HHI_GP_PLL_CNTL3, .def = 0xca463823 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) { .reg = HHI_GP_PLL_CNTL4, .def = 0x0286a027 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) { .reg = HHI_GP_PLL_CNTL5, .def = 0x00003000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) PLL_PARAMS(182, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) static struct clk_regmap meson8m2_gp_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .reg_off = HHI_GP_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .reg_off = HHI_GP_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .reg_off = HHI_GP_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .reg_off = HHI_GP_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .reg_off = HHI_GP_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .table = meson8m2_gp_pll_params_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .init_regs = meson8m2_gp_pll_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .init_count = ARRAY_SIZE(meson8m2_gp_pll_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .name = "gp_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) static struct clk_regmap meson8m2_gp_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .offset = HHI_GP_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .name = "gp_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) &meson8m2_gp_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) &meson8b_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) &meson8b_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) &meson8b_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) &meson8b_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) &meson8b_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) &meson8b_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) &meson8b_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) &meson8m2_gp_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static struct clk_regmap meson8b_vpu_0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .name = "vpu_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .parent_hws = meson8b_vpu_0_1_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static struct clk_regmap meson8m2_vpu_0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .name = "vpu_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) static struct clk_regmap meson8b_vpu_0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .name = "vpu_0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) * meson8b and meson8m2 have different vpu_0_sels (with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) * different struct clk_hw). We fallback to the global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) * naming string mechanism so vpu_0_div picks up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) * appropriate one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .name = "vpu_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) static struct clk_regmap meson8b_vpu_0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .name = "vpu_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) &meson8b_vpu_0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) static struct clk_regmap meson8b_vpu_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .name = "vpu_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .parent_hws = meson8b_vpu_0_1_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) static struct clk_regmap meson8m2_vpu_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .name = "vpu_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static struct clk_regmap meson8b_vpu_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .name = "vpu_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) * meson8b and meson8m2 have different vpu_1_sels (with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) * different struct clk_hw). We fallback to the global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) * naming string mechanism so vpu_1_div picks up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) * appropriate one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .name = "vpu_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) static struct clk_regmap meson8b_vpu_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .name = "vpu_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) &meson8b_vpu_1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) * The VPU clock has two two identical clock trees (vpu_0 and vpu_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) * actually manage this glitch-free mux because it does top-to-bottom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) * updates the each clock tree and switches to the "inactive" one when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) * CLK_SET_RATE_GATE is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) * Meson8 only has vpu_0 and no glitch-free mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) static struct clk_regmap meson8b_vpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .name = "vpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) &meson8b_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) &meson8b_vpu_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) static const struct clk_hw *meson8b_vdec_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) &meson8b_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) &meson8b_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) &meson8b_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) &meson8b_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) &meson8b_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) &meson8b_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) static struct clk_regmap meson8b_vdec_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .name = "vdec_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .parent_hws = meson8b_vdec_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) static struct clk_regmap meson8b_vdec_1_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .name = "vdec_1_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) &meson8b_vdec_1_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) static struct clk_regmap meson8b_vdec_1_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .name = "vdec_1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) &meson8b_vdec_1_1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) static struct clk_regmap meson8b_vdec_1_2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .offset = HHI_VDEC3_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .name = "vdec_1_2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) &meson8b_vdec_1_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static struct clk_regmap meson8b_vdec_1_2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .offset = HHI_VDEC3_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .name = "vdec_1_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) &meson8b_vdec_1_2_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) static struct clk_regmap meson8b_vdec_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .offset = HHI_VDEC3_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .name = "vdec_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) &meson8b_vdec_1_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) &meson8b_vdec_1_2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) static struct clk_regmap meson8b_vdec_hcodec_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .name = "vdec_hcodec_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .parent_hws = meson8b_vdec_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) static struct clk_regmap meson8b_vdec_hcodec_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .name = "vdec_hcodec_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) &meson8b_vdec_hcodec_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static struct clk_regmap meson8b_vdec_hcodec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .name = "vdec_hcodec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) &meson8b_vdec_hcodec_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static struct clk_regmap meson8b_vdec_2_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .name = "vdec_2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .parent_hws = meson8b_vdec_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) static struct clk_regmap meson8b_vdec_2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .name = "vdec_2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) &meson8b_vdec_2_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) static struct clk_regmap meson8b_vdec_2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .name = "vdec_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) &meson8b_vdec_2_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) static struct clk_regmap meson8b_vdec_hevc_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .name = "vdec_hevc_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .parent_hws = meson8b_vdec_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static struct clk_regmap meson8b_vdec_hevc_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .name = "vdec_hevc_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) &meson8b_vdec_hevc_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static struct clk_regmap meson8b_vdec_hevc_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .name = "vdec_hevc_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) &meson8b_vdec_hevc_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) static struct clk_regmap meson8b_vdec_hevc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .name = "vdec_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) /* TODO: The second parent is currently unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) &meson8b_vdec_hevc_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) &meson8b_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) &meson8b_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) &meson8b_mpll2.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) static struct clk_regmap meson8b_cts_amclk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .offset = HHI_AUD_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .table = meson8b_cts_amclk_mux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .name = "cts_amclk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .parent_hws = meson8b_cts_amclk_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) static struct clk_regmap meson8b_cts_amclk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .data = &(struct clk_regmap_div_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .offset = HHI_AUD_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .name = "cts_amclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) &meson8b_cts_amclk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) static struct clk_regmap meson8b_cts_amclk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .offset = HHI_AUD_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .name = "cts_amclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) &meson8b_cts_amclk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) &meson8b_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) &meson8b_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) &meson8b_mpll2.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) static struct clk_regmap meson8b_cts_mclk_i958_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .offset = HHI_AUD_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .table = meson8b_cts_mclk_i958_mux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .name = "cts_mclk_i958_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) .parent_hws = meson8b_cts_mclk_i958_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) static struct clk_regmap meson8b_cts_mclk_i958_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .offset = HHI_AUD_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .name = "cts_mclk_i958_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) &meson8b_cts_mclk_i958_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) static struct clk_regmap meson8b_cts_mclk_i958 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .offset = HHI_AUD_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .name = "cts_mclk_i958",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) &meson8b_cts_mclk_i958_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) static struct clk_regmap meson8b_cts_i958 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .offset = HHI_AUD_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .shift = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .name = "cts_i958",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) &meson8b_cts_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) &meson8b_cts_mclk_i958.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) * The parent is specific to origin of the audio data. Let the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) * consumer choose the appropriate parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) #define MESON_GATE(_name, _reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) /* Everything Else (EE) domain gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) /* AIU gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) #define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /* Always On (AO) domain gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static struct clk_hw_onecell_data meson8_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) [CLKID_XTAL] = &meson8b_xtal.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) [CLKID_CLK81] = &meson8b_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) [CLKID_DDR] = &meson8b_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) [CLKID_DOS] = &meson8b_dos.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) [CLKID_ISA] = &meson8b_isa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) [CLKID_PL301] = &meson8b_pl301.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) [CLKID_PERIPHS] = &meson8b_periphs.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) [CLKID_SPICC] = &meson8b_spicc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) [CLKID_I2C] = &meson8b_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) [CLKID_RNG0] = &meson8b_rng0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) [CLKID_UART0] = &meson8b_uart0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) [CLKID_SDHC] = &meson8b_sdhc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) [CLKID_STREAM] = &meson8b_stream.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) [CLKID_SDIO] = &meson8b_sdio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) [CLKID_ABUF] = &meson8b_abuf.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) [CLKID_SPI] = &meson8b_spi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) [CLKID_ETH] = &meson8b_eth.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) [CLKID_DEMUX] = &meson8b_demux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) [CLKID_IEC958] = &meson8b_iec958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) [CLKID_AMCLK] = &meson8b_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) [CLKID_MIXER] = &meson8b_mixer.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) [CLKID_ADC] = &meson8b_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) [CLKID_BLKMV] = &meson8b_blkmv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) [CLKID_AIU] = &meson8b_aiu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) [CLKID_UART1] = &meson8b_uart1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) [CLKID_G2D] = &meson8b_g2d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) [CLKID_USB0] = &meson8b_usb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) [CLKID_USB1] = &meson8b_usb1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) [CLKID_RESET] = &meson8b_reset.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) [CLKID_NAND] = &meson8b_nand.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) [CLKID_USB] = &meson8b_usb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) [CLKID_VDIN1] = &meson8b_vdin1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) [CLKID_EFUSE] = &meson8b_efuse.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) [CLKID_DVIN] = &meson8b_dvin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) [CLKID_UART2] = &meson8b_uart2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) [CLKID_SANA] = &meson8b_sana.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) [CLKID_ENC480P] = &meson8b_enc480p.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) [CLKID_RNG1] = &meson8b_rng1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) [CLKID_EDP] = &meson8b_edp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) [CLKID_MPLL0] = &meson8b_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) [CLKID_MPLL1] = &meson8b_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) [CLKID_MPLL2] = &meson8b_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) [CLKID_APB] = &meson8b_apb_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) [CLKID_MALI] = &meson8b_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) [CLKID_VPU] = &meson8b_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) [CLK_NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .num = CLK_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) [CLKID_XTAL] = &meson8b_xtal.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) [CLKID_CLK81] = &meson8b_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) [CLKID_DDR] = &meson8b_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) [CLKID_DOS] = &meson8b_dos.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) [CLKID_ISA] = &meson8b_isa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) [CLKID_PL301] = &meson8b_pl301.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) [CLKID_PERIPHS] = &meson8b_periphs.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) [CLKID_SPICC] = &meson8b_spicc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) [CLKID_I2C] = &meson8b_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) [CLKID_RNG0] = &meson8b_rng0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) [CLKID_UART0] = &meson8b_uart0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) [CLKID_SDHC] = &meson8b_sdhc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) [CLKID_STREAM] = &meson8b_stream.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) [CLKID_SDIO] = &meson8b_sdio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) [CLKID_ABUF] = &meson8b_abuf.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) [CLKID_SPI] = &meson8b_spi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) [CLKID_ETH] = &meson8b_eth.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) [CLKID_DEMUX] = &meson8b_demux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) [CLKID_IEC958] = &meson8b_iec958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) [CLKID_AMCLK] = &meson8b_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) [CLKID_MIXER] = &meson8b_mixer.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) [CLKID_ADC] = &meson8b_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) [CLKID_BLKMV] = &meson8b_blkmv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) [CLKID_AIU] = &meson8b_aiu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) [CLKID_UART1] = &meson8b_uart1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) [CLKID_G2D] = &meson8b_g2d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) [CLKID_USB0] = &meson8b_usb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) [CLKID_USB1] = &meson8b_usb1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) [CLKID_RESET] = &meson8b_reset.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) [CLKID_NAND] = &meson8b_nand.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) [CLKID_USB] = &meson8b_usb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) [CLKID_VDIN1] = &meson8b_vdin1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) [CLKID_EFUSE] = &meson8b_efuse.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) [CLKID_DVIN] = &meson8b_dvin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) [CLKID_UART2] = &meson8b_uart2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) [CLKID_SANA] = &meson8b_sana.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) [CLKID_ENC480P] = &meson8b_enc480p.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) [CLKID_RNG1] = &meson8b_rng1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) [CLKID_EDP] = &meson8b_edp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) [CLKID_MPLL0] = &meson8b_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) [CLKID_MPLL1] = &meson8b_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) [CLKID_MPLL2] = &meson8b_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) [CLKID_APB] = &meson8b_apb_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) [CLKID_MALI_0] = &meson8b_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) [CLKID_MALI_1] = &meson8b_mali_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) [CLKID_MALI] = &meson8b_mali.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) [CLKID_VPU_0] = &meson8b_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) [CLKID_VPU_1] = &meson8b_vpu_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) [CLKID_VPU] = &meson8b_vpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) [CLK_NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) .num = CLK_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) [CLKID_XTAL] = &meson8b_xtal.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) [CLKID_CLK81] = &meson8b_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) [CLKID_DDR] = &meson8b_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) [CLKID_DOS] = &meson8b_dos.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) [CLKID_ISA] = &meson8b_isa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) [CLKID_PL301] = &meson8b_pl301.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) [CLKID_PERIPHS] = &meson8b_periphs.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) [CLKID_SPICC] = &meson8b_spicc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) [CLKID_I2C] = &meson8b_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) [CLKID_RNG0] = &meson8b_rng0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) [CLKID_UART0] = &meson8b_uart0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) [CLKID_SDHC] = &meson8b_sdhc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) [CLKID_STREAM] = &meson8b_stream.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) [CLKID_SDIO] = &meson8b_sdio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) [CLKID_ABUF] = &meson8b_abuf.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) [CLKID_SPI] = &meson8b_spi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) [CLKID_ETH] = &meson8b_eth.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) [CLKID_DEMUX] = &meson8b_demux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) [CLKID_IEC958] = &meson8b_iec958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) [CLKID_AMCLK] = &meson8b_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) [CLKID_MIXER] = &meson8b_mixer.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) [CLKID_ADC] = &meson8b_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) [CLKID_BLKMV] = &meson8b_blkmv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) [CLKID_AIU] = &meson8b_aiu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) [CLKID_UART1] = &meson8b_uart1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) [CLKID_G2D] = &meson8b_g2d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) [CLKID_USB0] = &meson8b_usb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) [CLKID_USB1] = &meson8b_usb1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) [CLKID_RESET] = &meson8b_reset.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) [CLKID_NAND] = &meson8b_nand.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) [CLKID_USB] = &meson8b_usb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) [CLKID_VDIN1] = &meson8b_vdin1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) [CLKID_EFUSE] = &meson8b_efuse.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) [CLKID_DVIN] = &meson8b_dvin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) [CLKID_UART2] = &meson8b_uart2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) [CLKID_SANA] = &meson8b_sana.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) [CLKID_ENC480P] = &meson8b_enc480p.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) [CLKID_RNG1] = &meson8b_rng1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) [CLKID_EDP] = &meson8b_edp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) [CLKID_MPLL0] = &meson8b_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) [CLKID_MPLL1] = &meson8b_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) [CLKID_MPLL2] = &meson8b_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) [CLKID_APB] = &meson8b_apb_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) [CLKID_MALI_0] = &meson8b_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) [CLKID_MALI_1] = &meson8b_mali_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) [CLKID_MALI] = &meson8b_mali.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) [CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) [CLKID_VPU_0] = &meson8b_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) [CLKID_VPU_1] = &meson8b_vpu_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) [CLKID_VPU] = &meson8b_vpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) [CLK_NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) .num = CLK_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) static struct clk_regmap *const meson8b_clk_regmaps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) &meson8b_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) &meson8b_ddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) &meson8b_dos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) &meson8b_isa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) &meson8b_pl301,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) &meson8b_periphs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) &meson8b_spicc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) &meson8b_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) &meson8b_sar_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) &meson8b_smart_card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) &meson8b_rng0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) &meson8b_uart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) &meson8b_sdhc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) &meson8b_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) &meson8b_async_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) &meson8b_sdio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) &meson8b_abuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) &meson8b_hiu_iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) &meson8b_assist_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) &meson8b_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) &meson8b_i2s_spdif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) &meson8b_eth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) &meson8b_demux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) &meson8b_aiu_glue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) &meson8b_iec958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) &meson8b_i2s_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) &meson8b_amclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) &meson8b_aififo2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) &meson8b_mixer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) &meson8b_mixer_iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) &meson8b_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) &meson8b_blkmv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) &meson8b_aiu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) &meson8b_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) &meson8b_g2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) &meson8b_usb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) &meson8b_usb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) &meson8b_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) &meson8b_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) &meson8b_dos_parser,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) &meson8b_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) &meson8b_vdin1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) &meson8b_ahb_arb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) &meson8b_efuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) &meson8b_boot_rom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) &meson8b_ahb_data_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) &meson8b_ahb_ctrl_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) &meson8b_hdmi_intr_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) &meson8b_hdmi_pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) &meson8b_usb1_ddr_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) &meson8b_usb0_ddr_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) &meson8b_mmc_pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) &meson8b_dvin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) &meson8b_uart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) &meson8b_sana,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) &meson8b_vpu_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) &meson8b_sec_ahb_ahb3_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) &meson8b_clk81_a9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) &meson8b_vclk2_venci0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) &meson8b_vclk2_venci1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) &meson8b_vclk2_vencp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) &meson8b_vclk2_vencp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) &meson8b_gclk_venci_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) &meson8b_gclk_vencp_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) &meson8b_dac_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) &meson8b_aoclk_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) &meson8b_iec958_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) &meson8b_enc480p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) &meson8b_rng1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) &meson8b_gclk_vencl_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) &meson8b_vclk2_venclmcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) &meson8b_vclk2_vencl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) &meson8b_vclk2_other,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) &meson8b_edp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) &meson8b_ao_media_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) &meson8b_ao_ahb_sram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) &meson8b_ao_ahb_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) &meson8b_ao_iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) &meson8b_mpeg_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) &meson8b_mpeg_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) &meson8b_mpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) &meson8b_mpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) &meson8b_mpll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) &meson8b_mpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) &meson8b_mpll1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) &meson8b_mpll2_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) &meson8b_fixed_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) &meson8b_sys_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) &meson8b_cpu_in_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) &meson8b_cpu_scale_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) &meson8b_cpu_scale_out_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) &meson8b_cpu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) &meson8b_mpll_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) &meson8b_fclk_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) &meson8b_fclk_div3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) &meson8b_fclk_div4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) &meson8b_fclk_div5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) &meson8b_fclk_div7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) &meson8b_nand_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) &meson8b_nand_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) &meson8b_nand_clk_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) &meson8b_fixed_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) &meson8b_hdmi_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) &meson8b_sys_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) &meson8b_apb_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) &meson8b_apb_clk_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) &meson8b_periph_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) &meson8b_periph_clk_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) &meson8b_axi_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) &meson8b_axi_clk_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) &meson8b_l2_dram_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) &meson8b_l2_dram_clk_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) &meson8b_hdmi_pll_lvds_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) &meson8b_hdmi_pll_hdmi_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) &meson8b_vid_pll_in_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) &meson8b_vid_pll_in_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) &meson8b_vid_pll_pre_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) &meson8b_vid_pll_post_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) &meson8b_vid_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) &meson8b_vid_pll_final_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) &meson8b_vclk_in_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) &meson8b_vclk_in_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) &meson8b_vclk_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) &meson8b_vclk_div1_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) &meson8b_vclk_div2_div_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) &meson8b_vclk_div4_div_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) &meson8b_vclk_div6_div_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) &meson8b_vclk_div12_div_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) &meson8b_vclk2_in_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) &meson8b_vclk2_clk_in_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) &meson8b_vclk2_clk_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) &meson8b_vclk2_div1_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) &meson8b_vclk2_div2_div_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) &meson8b_vclk2_div4_div_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) &meson8b_vclk2_div6_div_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) &meson8b_vclk2_div12_div_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) &meson8b_cts_enct_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) &meson8b_cts_enct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) &meson8b_cts_encp_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) &meson8b_cts_encp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) &meson8b_cts_enci_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) &meson8b_cts_enci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) &meson8b_hdmi_tx_pixel_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) &meson8b_hdmi_tx_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) &meson8b_cts_encl_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) &meson8b_cts_encl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) &meson8b_cts_vdac0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) &meson8b_cts_vdac0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) &meson8b_hdmi_sys_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) &meson8b_hdmi_sys_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) &meson8b_hdmi_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) &meson8b_mali_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) &meson8b_mali_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) &meson8b_mali_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) &meson8b_mali_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) &meson8b_mali_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) &meson8b_mali_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) &meson8b_mali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) &meson8m2_gp_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) &meson8m2_gp_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) &meson8b_vpu_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) &meson8m2_vpu_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) &meson8b_vpu_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) &meson8b_vpu_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) &meson8b_vpu_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) &meson8m2_vpu_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) &meson8b_vpu_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) &meson8b_vpu_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) &meson8b_vpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) &meson8b_vdec_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) &meson8b_vdec_1_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) &meson8b_vdec_1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) &meson8b_vdec_1_2_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) &meson8b_vdec_1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) &meson8b_vdec_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) &meson8b_vdec_hcodec_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) &meson8b_vdec_hcodec_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) &meson8b_vdec_hcodec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) &meson8b_vdec_2_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) &meson8b_vdec_2_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) &meson8b_vdec_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) &meson8b_vdec_hevc_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) &meson8b_vdec_hevc_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) &meson8b_vdec_hevc_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) &meson8b_vdec_hevc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) &meson8b_cts_amclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) &meson8b_cts_amclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) &meson8b_cts_amclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) &meson8b_cts_mclk_i958_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) &meson8b_cts_mclk_i958_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) &meson8b_cts_mclk_i958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) &meson8b_cts_i958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) static const struct meson8b_clk_reset_line {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) bool active_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) } meson8b_clk_reset_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) .reg = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) .bit_idx = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) .reg = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) .bit_idx = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) [CLKC_RESET_SCU_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) .reg = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) .bit_idx = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) [CLKC_RESET_CPU3_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) .reg = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) .bit_idx = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) [CLKC_RESET_CPU2_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) .reg = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) .bit_idx = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) [CLKC_RESET_CPU1_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) .reg = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) .bit_idx = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) [CLKC_RESET_CPU0_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) .reg = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) [CLKC_RESET_A5_GLOBAL_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) .reg = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) .bit_idx = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) [CLKC_RESET_A5_AXI_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) .reg = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) .bit_idx = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) [CLKC_RESET_A5_ABP_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) .reg = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) .bit_idx = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) .reg = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) .bit_idx = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) .reg = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) .bit_idx = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) .reg = HHI_VID_DIVIDER_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) .reg = HHI_VID_DIVIDER_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) .bit_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) .active_low = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) .reg = HHI_VID_DIVIDER_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) .active_low = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) .reg = HHI_VID_DIVIDER_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) .active_low = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) struct meson8b_clk_reset *meson8b_clk_reset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) container_of(rcdev, struct meson8b_clk_reset, reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) const struct meson8b_clk_reset_line *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) unsigned int value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) reset = &meson8b_clk_reset_bits[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) if (assert != reset->active_low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) value = BIT(reset->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) spin_lock_irqsave(&meson_clk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) BIT(reset->bit_idx), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) spin_unlock_irqrestore(&meson_clk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) return meson8b_clk_reset_update(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) return meson8b_clk_reset_update(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) static const struct reset_control_ops meson8b_clk_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) .assert = meson8b_clk_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) .deassert = meson8b_clk_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) struct meson8b_nb_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) struct clk_hw *cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) struct meson8b_nb_data *nb_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) container_of(nb, struct meson8b_nb_data, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) struct clk_hw *parent_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) /* xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) /* cpu_scale_out_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) return notifier_from_errno(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) static struct meson8b_nb_data meson8b_cpu_nb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) .nb.notifier_call = meson8b_cpu_clk_notifier_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) static const struct regmap_config clkc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) static void __init meson8b_clkc_init_common(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) struct clk_hw_onecell_data *clk_hw_onecell_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) struct meson8b_clk_reset *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) const char *notifier_clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) struct clk *notifier_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) map = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) pr_info("failed to get HHI regmap - Trying obsolete regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) /* Generic clocks, PLLs and some of the reset-bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) clk_base = of_iomap(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) if (!clk_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) pr_err("%s: Unable to map clk base\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) if (IS_ERR(map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) if (!rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) /* Reset Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) rstc->regmap = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) rstc->reset.ops = &meson8b_clk_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) rstc->reset.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) ret = reset_controller_register(&rstc->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) pr_err("%s: Failed to register clkc reset controller: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) /* Populate regmap for the regmap backed clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) meson8b_clk_regmaps[i]->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) * always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) * XTAL clock as input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) if (!IS_ERR(of_clk_get_by_name(np, "xtal")))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) i = CLKID_PLL_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) i = CLKID_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) /* register all clks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) for (; i < CLK_NR_CLKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) /* array might be sparse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) if (!clk_hw_onecell_data->hws[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) * FIXME we shouldn't program the muxes in notifier handlers. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) * tricky programming sequence will be handled by the forthcoming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) * coordinated clock rates mechanism once that feature is released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) notifier_clk = __clk_lookup(notifier_clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) pr_err("%s: failed to register the CPU clock notifier\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) clk_hw_onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) pr_err("%s: failed to register clock provider\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) static void __init meson8_clkc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) static void __init meson8b_clkc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) static void __init meson8m2_clkc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) meson8_clkc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) meson8b_clkc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) meson8m2_clkc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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