Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2016 AmLogic, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Michael Turquette <mturquette@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef __GXBB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define __GXBB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Clock controller register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Register offsets from the data sheet are listed in comment blocks below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Those offsets must be multiplied by 4 before adding them to the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * to get the right value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SCR				0x2C /* 0x0b offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TIMEOUT_VALUE			0x3c /* 0x0f offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define HHI_GP0_PLL_CNTL		0x40 /* 0x10 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define HHI_GP0_PLL_CNTL2		0x44 /* 0x11 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define HHI_GP0_PLL_CNTL3		0x48 /* 0x12 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define HHI_GP0_PLL_CNTL4		0x4c /* 0x13 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define	HHI_GP0_PLL_CNTL5		0x50 /* 0x14 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define	HHI_GP0_PLL_CNTL1		0x58 /* 0x16 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define HHI_XTAL_DIVN_CNTL		0xbc /* 0x2f offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define HHI_TIMER90K			0xec /* 0x3b offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define HHI_MEM_PD_REG0			0x100 /* 0x40 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HHI_MEM_PD_REG1			0x104 /* 0x41 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define HHI_VPU_MEM_PD_REG1		0x108 /* 0x42 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define HHI_VIID_CLK_DIV		0x128 /* 0x4a offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define HHI_VIID_CLK_CNTL		0x12c /* 0x4b offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define HHI_GCLK_MPEG0			0x140 /* 0x50 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define HHI_GCLK_MPEG1			0x144 /* 0x51 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define HHI_GCLK_MPEG2			0x148 /* 0x52 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define HHI_GCLK_OTHER			0x150 /* 0x54 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define HHI_SYS_OSCIN_CNTL		0x158 /* 0x56 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define HHI_SYS_CPU_RESET_CNTL		0x160 /* 0x58 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define HHI_VID_CLK_DIV			0x164 /* 0x59 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define HHI_AUD_CLK_CNTL		0x178 /* 0x5e offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define HHI_AUD_CLK_CNTL2		0x190 /* 0x64 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define HHI_VID_CLK_CNTL2		0x194 /* 0x65 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define HHI_VID_PLL_CLK_DIV		0x1a0 /* 0x68 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define HHI_AUD_CLK_CNTL3		0x1a4 /* 0x69 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define HHI_MALI_CLK_CNTL		0x1b0 /* 0x6c offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define HHI_VPU_CLK_CNTL		0x1bC /* 0x6f offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define HHI_HDMI_CLK_CNTL		0x1CC /* 0x73 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define HHI_VDEC_CLK_CNTL		0x1E0 /* 0x78 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define HHI_VDEC2_CLK_CNTL		0x1E4 /* 0x79 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define HHI_VDEC3_CLK_CNTL		0x1E8 /* 0x7a offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define HHI_VDEC4_CLK_CNTL		0x1EC /* 0x7b offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define HHI_HDCP22_CLK_CNTL		0x1F0 /* 0x7c offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define HHI_VAPBCLK_CNTL		0x1F4 /* 0x7d offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define HHI_VPU_CLKB_CNTL		0x20C /* 0x83 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define HHI_USB_CLK_CNTL		0x220 /* 0x88 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define HHI_32K_CLK_CNTL		0x224 /* 0x89 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define HHI_GEN_CLK_CNTL		0x228 /* 0x8a offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define HHI_PCM_CLK_CNTL		0x258 /* 0x96 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define HHI_NAND_CLK_CNTL		0x25C /* 0x97 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define HHI_SD_EMMC_CLK_CNTL		0x264 /* 0x99 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define HHI_MPLL_CNTL2			0x284 /* 0xa1 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define HHI_MPLL_CNTL3			0x288 /* 0xa2 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define HHI_MPLL_CNTL4			0x28C /* 0xa3 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define HHI_MPLL_CNTL5			0x290 /* 0xa4 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define HHI_MPLL_CNTL6			0x294 /* 0xa5 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define HHI_MPLL_CNTL7			0x298 /* MP0, 0xa6 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define HHI_MPLL_CNTL8			0x29C /* MP1, 0xa7 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define HHI_MPLL_CNTL9			0x2A0 /* MP2, 0xa8 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define HHI_MPLL_CNTL10			0x2A4 /* MP2, 0xa9 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define HHI_MPLL3_CNTL0			0x2E0 /* 0xb8 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define HHI_MPLL3_CNTL1			0x2E4 /* 0xb9 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define HHI_VDAC_CNTL0			0x2F4 /* 0xbd offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define HHI_VDAC_CNTL1			0x2F8 /* 0xbe offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define HHI_SYS_PLL_CNTL2		0x304 /* 0xc1 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define HHI_SYS_PLL_CNTL3		0x308 /* 0xc2 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define HHI_SYS_PLL_CNTL4		0x30c /* 0xc3 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define HHI_SYS_PLL_CNTL5		0x310 /* 0xc4 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define HHI_DPLL_TOP_I			0x318 /* 0xc6 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define HHI_DPLL_TOP2_I			0x31C /* 0xc7 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define HHI_HDMI_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define HHI_HDMI_PLL_CNTL2		0x324 /* 0xc9 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define HHI_HDMI_PLL_CNTL3		0x328 /* 0xca offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HHI_HDMI_PLL_CNTL4		0x32C /* 0xcb offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HHI_HDMI_PLL_CNTL5		0x330 /* 0xcc offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HHI_HDMI_PLL_CNTL6		0x334 /* 0xcd offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HHI_HDMI_PLL_CNTL_I		0x338 /* 0xce offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HHI_HDMI_PLL_CNTL7		0x33C /* 0xcf offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HHI_HDMI_PHY_CNTL0		0x3A0 /* 0xe8 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HHI_HDMI_PHY_CNTL1		0x3A4 /* 0xe9 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HHI_HDMI_PHY_CNTL2		0x3A8 /* 0xea offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HHI_HDMI_PHY_CNTL3		0x3AC /* 0xeb offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HHI_VID_LOCK_CLK_CNTL		0x3C8 /* 0xf2 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HHI_BT656_CLK_CNTL		0x3D4 /* 0xf5 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HHI_SAR_CLK_CNTL		0x3D8 /* 0xf6 offset in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * CLKID index values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * These indices are entirely contrived and do not map onto the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * It has now been decided to expose everything by default in the DT header:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * to expose, such as the internal muxes and dividers of composite clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * will remain defined here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLKID_MPEG_SEL		  10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLKID_MPEG_DIV		  11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLKID_SAR_ADC_DIV	  99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLKID_MALI_0_DIV	  101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLKID_MALI_1_DIV	  104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLKID_CTS_AMCLK_SEL	  108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLKID_CTS_AMCLK_DIV	  109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLKID_CTS_MCLK_I958_SEL	  111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLKID_CTS_MCLK_I958_DIV	  112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLKID_32K_CLK_SEL	  115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLKID_32K_CLK_DIV	  116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLKID_SD_EMMC_A_CLK0_SEL  117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLKID_SD_EMMC_A_CLK0_DIV  118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLKID_SD_EMMC_B_CLK0_SEL  120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLKID_SD_EMMC_B_CLK0_DIV  121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLKID_SD_EMMC_C_CLK0_SEL  123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLKID_SD_EMMC_C_CLK0_DIV  124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLKID_VPU_0_DIV		  127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLKID_VPU_1_DIV		  130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLKID_VAPB_0_DIV	  134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLKID_VAPB_1_DIV	  137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLKID_HDMI_PLL_PRE_MULT	  141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLKID_MPLL0_DIV		  142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLKID_MPLL1_DIV		  143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLKID_MPLL2_DIV		  144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLKID_MPLL_PREDIV	  145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLKID_FCLK_DIV2_DIV	  146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLKID_FCLK_DIV3_DIV	  147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLKID_FCLK_DIV4_DIV	  148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLKID_FCLK_DIV5_DIV	  149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLKID_FCLK_DIV7_DIV	  150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLKID_VDEC_1_SEL	  151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLKID_VDEC_1_DIV	  152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLKID_VDEC_HEVC_SEL	  154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLKID_VDEC_HEVC_DIV	  155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLKID_GEN_CLK_SEL	  157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLKID_GEN_CLK_DIV	  158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLKID_FIXED_PLL_DCO	  160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLKID_HDMI_PLL_DCO	  161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLKID_HDMI_PLL_OD	  162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLKID_HDMI_PLL_OD2	  163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLKID_SYS_PLL_DCO	  164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLKID_GP0_PLL_DCO	  165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLKID_VID_PLL_SEL	  167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLKID_VID_PLL_DIV	  168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLKID_VCLK_SEL		  169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLKID_VCLK2_SEL		  170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLKID_VCLK_INPUT	  171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLKID_VCLK2_INPUT	  172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLKID_VCLK_DIV		  173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLKID_VCLK2_DIV		  174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLKID_VCLK_DIV2_EN	  177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLKID_VCLK_DIV4_EN	  178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLKID_VCLK_DIV6_EN	  179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLKID_VCLK_DIV12_EN	  180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLKID_VCLK2_DIV2_EN	  181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLKID_VCLK2_DIV4_EN	  182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLKID_VCLK2_DIV6_EN	  183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLKID_VCLK2_DIV12_EN	  184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLKID_CTS_ENCI_SEL	  195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLKID_CTS_ENCP_SEL	  196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLKID_CTS_VDAC_SEL	  197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLKID_HDMI_TX_SEL	  198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLKID_HDMI_SEL		  203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLKID_HDMI_DIV		  204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define NR_CLKS			  207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* include the CLKIDs that have been made part of the DT binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #include <dt-bindings/clock/gxbb-clkc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif /* __GXBB_H */