^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 AmLogic, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Michael Turquette <mturquette@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "gxbb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-mpll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "meson-eeclk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "vid-pll-div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static DEFINE_SPINLOCK(meson_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PLL_PARAMS(32, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PLL_PARAMS(33, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PLL_PARAMS(34, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PLL_PARAMS(35, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PLL_PARAMS(36, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PLL_PARAMS(37, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PLL_PARAMS(38, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PLL_PARAMS(39, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PLL_PARAMS(40, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PLL_PARAMS(41, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PLL_PARAMS(42, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PLL_PARAMS(43, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PLL_PARAMS(44, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PLL_PARAMS(45, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PLL_PARAMS(46, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PLL_PARAMS(47, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PLL_PARAMS(48, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PLL_PARAMS(49, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PLL_PARAMS(50, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PLL_PARAMS(51, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PLL_PARAMS(52, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PLL_PARAMS(53, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PLL_PARAMS(54, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PLL_PARAMS(55, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PLL_PARAMS(56, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PLL_PARAMS(57, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PLL_PARAMS(58, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PLL_PARAMS(59, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PLL_PARAMS(60, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PLL_PARAMS(61, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PLL_PARAMS(62, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct pll_params_table gxl_gp0_pll_params_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PLL_PARAMS(42, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PLL_PARAMS(43, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PLL_PARAMS(44, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PLL_PARAMS(45, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PLL_PARAMS(46, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PLL_PARAMS(47, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PLL_PARAMS(48, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PLL_PARAMS(49, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PLL_PARAMS(50, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PLL_PARAMS(51, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PLL_PARAMS(52, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PLL_PARAMS(53, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PLL_PARAMS(54, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PLL_PARAMS(55, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PLL_PARAMS(56, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PLL_PARAMS(57, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PLL_PARAMS(58, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PLL_PARAMS(59, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PLL_PARAMS(60, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PLL_PARAMS(61, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PLL_PARAMS(62, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PLL_PARAMS(63, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PLL_PARAMS(64, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PLL_PARAMS(65, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PLL_PARAMS(66, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct clk_regmap gxbb_fixed_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .reg_off = HHI_MPLL_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = "fixed_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct clk_regmap gxbb_fixed_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .offset = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "fixed_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) &gxbb_fixed_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * This clock won't ever change at runtime so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * CLK_SET_RATE_PARENT is not required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .mult = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "hdmi_pll_pre_mult",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct clk_regmap gxbb_hdmi_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .reg_off = HHI_HDMI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .reg_off = HHI_HDMI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .reg_off = HHI_HDMI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .reg_off = HHI_HDMI_PLL_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .reg_off = HHI_HDMI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .reg_off = HHI_HDMI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .name = "hdmi_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) &gxbb_hdmi_pll_pre_mult.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Display directly handle hdmi pll registers ATM, we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * NOCACHE to keep our view of the clock as accurate as possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct clk_regmap gxl_hdmi_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .reg_off = HHI_HDMI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .reg_off = HHI_HDMI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .reg_off = HHI_HDMI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * On gxl, there is a register shift due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * instead which is defined at the same offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .reg_off = HHI_HDMI_PLL_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .width = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .reg_off = HHI_HDMI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .reg_off = HHI_HDMI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "hdmi_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Display directly handle hdmi pll registers ATM, we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * NOCACHE to keep our view of the clock as accurate as possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct clk_regmap gxbb_hdmi_pll_od = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .offset = HHI_HDMI_PLL_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .name = "hdmi_pll_od",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) &gxbb_hdmi_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct clk_regmap gxbb_hdmi_pll_od2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .offset = HHI_HDMI_PLL_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .shift = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .name = "hdmi_pll_od2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) &gxbb_hdmi_pll_od.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static struct clk_regmap gxbb_hdmi_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .offset = HHI_HDMI_PLL_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .name = "hdmi_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) &gxbb_hdmi_pll_od2.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct clk_regmap gxl_hdmi_pll_od = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .offset = HHI_HDMI_PLL_CNTL + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .shift = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .name = "hdmi_pll_od",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) &gxl_hdmi_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct clk_regmap gxl_hdmi_pll_od2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .offset = HHI_HDMI_PLL_CNTL + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .shift = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .name = "hdmi_pll_od2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &gxl_hdmi_pll_od.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct clk_regmap gxl_hdmi_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .offset = HHI_HDMI_PLL_CNTL + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .shift = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = "hdmi_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) &gxl_hdmi_pll_od2.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct clk_regmap gxbb_sys_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "sys_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct clk_regmap gxbb_sys_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .offset = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .name = "sys_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) &gxbb_sys_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct reg_sequence gxbb_gp0_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct clk_regmap gxbb_gp0_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .table = gxbb_gp0_pll_params_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .init_regs = gxbb_gp0_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .name = "gp0_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct reg_sequence gxl_gp0_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct clk_regmap gxl_gp0_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .reg_off = HHI_GP0_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .width = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .table = gxl_gp0_pll_params_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .init_regs = gxl_gp0_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .name = "gp0_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct clk_regmap gxbb_gp0_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .offset = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .name = "gp0_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * GXL and GXBB have different gp0_pll_dco (with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * different struct clk_hw). We fallback to the global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * naming string mechanism so gp0_pll picks up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * appropriate one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .name = "gp0_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct clk_fixed_factor gxbb_fclk_div2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .name = "fclk_div2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) &gxbb_fixed_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static struct clk_regmap gxbb_fclk_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .bit_idx = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .name = "fclk_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) &gxbb_fclk_div2_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static struct clk_fixed_factor gxbb_fclk_div3_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .div = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .name = "fclk_div3_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static struct clk_regmap gxbb_fclk_div3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .bit_idx = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .name = "fclk_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) &gxbb_fclk_div3_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * FIXME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * This clock, as fdiv2, is used by the SCPI FW and is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * by the platform to operate correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * Until the following condition are met, we need this clock to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * be marked as critical:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * a) The SCPI generic driver claims and enable all the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * it needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * b) CCF has a clock hand-off mechanism to make the sure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * clock stays on until the proper driver comes along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static struct clk_fixed_factor gxbb_fclk_div4_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .name = "fclk_div4_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static struct clk_regmap gxbb_fclk_div4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .bit_idx = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .name = "fclk_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) &gxbb_fclk_div4_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static struct clk_fixed_factor gxbb_fclk_div5_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .div = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .name = "fclk_div5_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static struct clk_regmap gxbb_fclk_div5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .bit_idx = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .name = "fclk_div5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) &gxbb_fclk_div5_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static struct clk_fixed_factor gxbb_fclk_div7_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .div = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .name = "fclk_div7_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static struct clk_regmap gxbb_fclk_div7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .bit_idx = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .name = "fclk_div7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) &gxbb_fclk_div7_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static struct clk_regmap gxbb_mpll_prediv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .offset = HHI_MPLL_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .name = "mpll_prediv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static struct clk_regmap gxbb_mpll0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .name = "mpll0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) &gxbb_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static struct clk_regmap gxl_mpll0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .name = "mpll0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) &gxbb_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static struct clk_regmap gxbb_mpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .offset = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .bit_idx = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .name = "mpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * GXL and GXBB have different SDM_EN registers. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * fallback to the global naming string mechanism so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * mpll0_div picks up the appropriate one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .name = "mpll0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static struct clk_regmap gxbb_mpll1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .reg_off = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .reg_off = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .reg_off = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .name = "mpll1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) &gxbb_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static struct clk_regmap gxbb_mpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .offset = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .bit_idx = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .name = "mpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static struct clk_regmap gxbb_mpll2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .reg_off = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .reg_off = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .reg_off = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .name = "mpll2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) &gxbb_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static struct clk_regmap gxbb_mpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .offset = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .bit_idx = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .name = "mpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static const struct clk_parent_data clk81_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) { .hw = &gxbb_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { .hw = &gxbb_mpll1.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) { .hw = &gxbb_mpll2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) { .hw = &gxbb_fclk_div4.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) { .hw = &gxbb_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) { .hw = &gxbb_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static struct clk_regmap gxbb_mpeg_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .table = mux_table_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .name = "mpeg_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * bits 14:12 selects from 8 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * fclk_div4, fclk_div3, fclk_div5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .parent_data = clk81_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .num_parents = ARRAY_SIZE(clk81_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static struct clk_regmap gxbb_mpeg_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .name = "mpeg_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) &gxbb_mpeg_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* the mother of dragons gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static struct clk_regmap gxbb_clk81 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .name = "clk81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) &gxbb_mpeg_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static struct clk_regmap gxbb_sar_adc_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .offset = HHI_SAR_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .name = "sar_adc_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* NOTE: The datasheet doesn't list the parents for bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) { .hw = &gxbb_clk81.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static struct clk_regmap gxbb_sar_adc_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .offset = HHI_SAR_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .name = "sar_adc_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) &gxbb_sar_adc_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static struct clk_regmap gxbb_sar_adc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .offset = HHI_SAR_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .name = "sar_adc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) &gxbb_sar_adc_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * muxed by a glitch-free switch. The CCF can manage this glitch-free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * mux because it does top-to-bottom updates the each clock tree and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) { .hw = &gxbb_gp0_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) { .hw = &gxbb_mpll2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) { .hw = &gxbb_mpll1.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) { .hw = &gxbb_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) { .hw = &gxbb_fclk_div4.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) { .hw = &gxbb_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) { .hw = &gxbb_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static struct clk_regmap gxbb_mali_0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .name = "mali_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .parent_data = gxbb_mali_0_1_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * Don't request the parent to change the rate because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * all GPU frequencies can be derived from the fclk_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * clocks and one special GP0_PLL setting. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * important because we need the MPLL clocks for audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static struct clk_regmap gxbb_mali_0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .name = "mali_0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) &gxbb_mali_0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static struct clk_regmap gxbb_mali_0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .name = "mali_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) &gxbb_mali_0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static struct clk_regmap gxbb_mali_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .name = "mali_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .parent_data = gxbb_mali_0_1_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * Don't request the parent to change the rate because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * all GPU frequencies can be derived from the fclk_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * clocks and one special GP0_PLL setting. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * important because we need the MPLL clocks for audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static struct clk_regmap gxbb_mali_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .name = "mali_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) &gxbb_mali_1_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static struct clk_regmap gxbb_mali_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .name = "mali_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) &gxbb_mali_1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static const struct clk_hw *gxbb_mali_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) &gxbb_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) &gxbb_mali_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static struct clk_regmap gxbb_mali = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .name = "mali",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .parent_hws = gxbb_mali_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static struct clk_regmap gxbb_cts_amclk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .offset = HHI_AUD_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .table = (u32[]){ 1, 2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .name = "cts_amclk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) &gxbb_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) &gxbb_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) &gxbb_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static struct clk_regmap gxbb_cts_amclk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .data = &(struct clk_regmap_div_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .offset = HHI_AUD_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .name = "cts_amclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) &gxbb_cts_amclk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static struct clk_regmap gxbb_cts_amclk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .offset = HHI_AUD_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .name = "cts_amclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) &gxbb_cts_amclk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static struct clk_regmap gxbb_cts_mclk_i958_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .offset = HHI_AUD_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .table = (u32[]){ 1, 2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .name = "cts_mclk_i958_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) &gxbb_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) &gxbb_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) &gxbb_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static struct clk_regmap gxbb_cts_mclk_i958_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .offset = HHI_AUD_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .name = "cts_mclk_i958_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) &gxbb_cts_mclk_i958_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static struct clk_regmap gxbb_cts_mclk_i958 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .offset = HHI_AUD_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .name = "cts_mclk_i958",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) &gxbb_cts_mclk_i958_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static struct clk_regmap gxbb_cts_i958 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .offset = HHI_AUD_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .shift = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .name = "cts_i958",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) &gxbb_cts_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) &gxbb_cts_mclk_i958.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) *The parent is specific to origin of the audio data. Let the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * consumer choose the appropriate parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * FIXME: This clock is provided by the ao clock controller but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * clock is not yet part of the binding of this controller, so string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * name must be use to set this parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) { .name = "cts_slow_oscin", .index = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) { .hw = &gxbb_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) { .hw = &gxbb_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static struct clk_regmap gxbb_32k_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .offset = HHI_32K_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .name = "32k_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .parent_data = gxbb_32k_clk_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static struct clk_regmap gxbb_32k_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .offset = HHI_32K_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .name = "32k_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) &gxbb_32k_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static struct clk_regmap gxbb_32k_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .offset = HHI_32K_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .bit_idx = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .name = "32k_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) &gxbb_32k_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) { .hw = &gxbb_fclk_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) { .hw = &gxbb_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) { .hw = &gxbb_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) { .hw = &gxbb_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * Following these parent clocks, we should also have had mpll2, mpll3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * and gp0_pll but these clocks are too precious to be used here. All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * the necessary rates for MMC and NAND operation can be acheived using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * xtal or fclk_div clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* SDIO clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .name = "sd_emmc_a_clk0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .parent_data = gxbb_sd_emmc_clk0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .name = "sd_emmc_a_clk0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) &gxbb_sd_emmc_a_clk0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .name = "sd_emmc_a_clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) &gxbb_sd_emmc_a_clk0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* SDcard clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .name = "sd_emmc_b_clk0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .parent_data = gxbb_sd_emmc_clk0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .name = "sd_emmc_b_clk0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) &gxbb_sd_emmc_b_clk0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .bit_idx = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .name = "sd_emmc_b_clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) &gxbb_sd_emmc_b_clk0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* EMMC/NAND clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .name = "sd_emmc_c_clk0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .parent_data = gxbb_sd_emmc_clk0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .name = "sd_emmc_c_clk0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) &gxbb_sd_emmc_c_clk0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .name = "sd_emmc_c_clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) &gxbb_sd_emmc_c_clk0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* VPU Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static const struct clk_hw *gxbb_vpu_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) &gxbb_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) &gxbb_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) &gxbb_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) &gxbb_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static struct clk_regmap gxbb_vpu_0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .name = "vpu_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * bits 9:10 selects from 4 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .parent_hws = gxbb_vpu_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static struct clk_regmap gxbb_vpu_0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .name = "vpu_0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static struct clk_regmap gxbb_vpu_0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .name = "vpu_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static struct clk_regmap gxbb_vpu_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .name = "vpu_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * bits 25:26 selects from 4 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .parent_hws = gxbb_vpu_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static struct clk_regmap gxbb_vpu_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .name = "vpu_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static struct clk_regmap gxbb_vpu_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .name = "vpu_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static struct clk_regmap gxbb_vpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .name = "vpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) * bit 31 selects from 2 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) * vpu_0 or vpu_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) &gxbb_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) &gxbb_vpu_1.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* VAPB Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static const struct clk_hw *gxbb_vapb_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) &gxbb_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) &gxbb_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) &gxbb_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) &gxbb_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static struct clk_regmap gxbb_vapb_0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .name = "vapb_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * bits 9:10 selects from 4 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .parent_hws = gxbb_vapb_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static struct clk_regmap gxbb_vapb_0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .name = "vapb_0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) &gxbb_vapb_0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static struct clk_regmap gxbb_vapb_0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .name = "vapb_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) &gxbb_vapb_0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static struct clk_regmap gxbb_vapb_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .name = "vapb_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) * bits 25:26 selects from 4 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .parent_hws = gxbb_vapb_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static struct clk_regmap gxbb_vapb_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .name = "vapb_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) &gxbb_vapb_1_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static struct clk_regmap gxbb_vapb_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .name = "vapb_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) &gxbb_vapb_1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static struct clk_regmap gxbb_vapb_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .name = "vapb_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * bit 31 selects from 2 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * vapb_0 or vapb_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) &gxbb_vapb_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) &gxbb_vapb_1.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static struct clk_regmap gxbb_vapb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .bit_idx = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .name = "vapb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* Video Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static struct clk_regmap gxbb_vid_pll_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .data = &(struct meson_vid_pll_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .val = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .reg_off = HHI_VID_PLL_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .width = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .reg_off = HHI_VID_PLL_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .name = "vid_pll_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .ops = &meson_vid_pll_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * GXL and GXBB have different hdmi_plls (with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * different struct clk_hw). We fallback to the global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) * naming string mechanism so vid_pll_div picks up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) * appropriate one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .name = "hdmi_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) { .hw = &gxbb_vid_pll_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) * GXL and GXBB have different hdmi_plls (with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) * different struct clk_hw). We fallback to the global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) * naming string mechanism so vid_pll_div picks up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) * appropriate one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) { .name = "hdmi_pll", .index = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) static struct clk_regmap gxbb_vid_pll_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .offset = HHI_VID_PLL_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .name = "vid_pll_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) * bit 18 selects from 2 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * vid_pll_div or hdmi_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .parent_data = gxbb_vid_pll_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static struct clk_regmap gxbb_vid_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .offset = HHI_VID_PLL_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .bit_idx = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .name = "vid_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) &gxbb_vid_pll_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static const struct clk_hw *gxbb_vclk_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) &gxbb_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) &gxbb_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) &gxbb_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) &gxbb_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) &gxbb_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) &gxbb_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) &gxbb_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) static struct clk_regmap gxbb_vclk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .name = "vclk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) * bits 16:18 selects from 8 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) * vid_pll, fclk_div4, fclk_div3, fclk_div5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) * vid_pll, fclk_div7, mp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .parent_hws = gxbb_vclk_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) static struct clk_regmap gxbb_vclk2_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .name = "vclk2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) * bits 16:18 selects from 8 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) * vid_pll, fclk_div4, fclk_div3, fclk_div5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * vid_pll, fclk_div7, mp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .parent_hws = gxbb_vclk_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static struct clk_regmap gxbb_vclk_input = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .bit_idx = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .name = "vclk_input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static struct clk_regmap gxbb_vclk2_input = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .bit_idx = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .name = "vclk2_input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static struct clk_regmap gxbb_vclk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .name = "vclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) &gxbb_vclk_input.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static struct clk_regmap gxbb_vclk2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .name = "vclk2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) &gxbb_vclk2_input.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static struct clk_regmap gxbb_vclk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .bit_idx = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .name = "vclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static struct clk_regmap gxbb_vclk2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .bit_idx = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .name = "vclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) static struct clk_regmap gxbb_vclk_div1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .name = "vclk_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) static struct clk_regmap gxbb_vclk_div2_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .name = "vclk_div2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static struct clk_regmap gxbb_vclk_div4_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .bit_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .name = "vclk_div4_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) static struct clk_regmap gxbb_vclk_div6_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .bit_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .name = "vclk_div6_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static struct clk_regmap gxbb_vclk_div12_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .bit_idx = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .name = "vclk_div12_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static struct clk_regmap gxbb_vclk2_div1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .name = "vclk2_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) static struct clk_regmap gxbb_vclk2_div2_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .name = "vclk2_div2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) static struct clk_regmap gxbb_vclk2_div4_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .bit_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .name = "vclk2_div4_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) static struct clk_regmap gxbb_vclk2_div6_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .bit_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .name = "vclk2_div6_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) static struct clk_regmap gxbb_vclk2_div12_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .bit_idx = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .name = "vclk2_div12_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static struct clk_fixed_factor gxbb_vclk_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .name = "vclk_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) &gxbb_vclk_div2_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static struct clk_fixed_factor gxbb_vclk_div4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .name = "vclk_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) &gxbb_vclk_div4_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static struct clk_fixed_factor gxbb_vclk_div6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .div = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .name = "vclk_div6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) &gxbb_vclk_div6_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) static struct clk_fixed_factor gxbb_vclk_div12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .div = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .name = "vclk_div12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) &gxbb_vclk_div12_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) static struct clk_fixed_factor gxbb_vclk2_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .name = "vclk2_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) &gxbb_vclk2_div2_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) static struct clk_fixed_factor gxbb_vclk2_div4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .name = "vclk2_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) &gxbb_vclk2_div4_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static struct clk_fixed_factor gxbb_vclk2_div6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .div = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .name = "vclk2_div6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) &gxbb_vclk2_div6_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) static struct clk_fixed_factor gxbb_vclk2_div12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .div = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .name = "vclk2_div12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) &gxbb_vclk2_div12_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static const struct clk_hw *gxbb_cts_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) &gxbb_vclk_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) &gxbb_vclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) &gxbb_vclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) &gxbb_vclk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) &gxbb_vclk_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) &gxbb_vclk2_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) &gxbb_vclk2_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) &gxbb_vclk2_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) &gxbb_vclk2_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) &gxbb_vclk2_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) static struct clk_regmap gxbb_cts_enci_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .table = mux_table_cts_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .name = "cts_enci_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .parent_hws = gxbb_cts_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) static struct clk_regmap gxbb_cts_encp_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .table = mux_table_cts_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .name = "cts_encp_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .parent_hws = gxbb_cts_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) static struct clk_regmap gxbb_cts_vdac_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .table = mux_table_cts_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .name = "cts_vdac_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .parent_hws = gxbb_cts_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) /* TOFIX: add support for cts_tcon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) &gxbb_vclk_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) &gxbb_vclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) &gxbb_vclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) &gxbb_vclk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) &gxbb_vclk_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) &gxbb_vclk2_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) &gxbb_vclk2_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) &gxbb_vclk2_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) &gxbb_vclk2_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) &gxbb_vclk2_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) static struct clk_regmap gxbb_hdmi_tx_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .table = mux_table_hdmi_tx_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .name = "hdmi_tx_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) * bits 31:28 selects from 12 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) * cts_tcon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) static struct clk_regmap gxbb_cts_enci = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .name = "cts_enci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) &gxbb_cts_enci_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) static struct clk_regmap gxbb_cts_encp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .bit_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .name = "cts_encp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) &gxbb_cts_encp_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static struct clk_regmap gxbb_cts_vdac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .bit_idx = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .name = "cts_vdac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) &gxbb_cts_vdac_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) static struct clk_regmap gxbb_hdmi_tx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .bit_idx = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .name = "hdmi_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) &gxbb_hdmi_tx_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) /* HDMI Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) { .hw = &gxbb_fclk_div4.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) { .hw = &gxbb_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) { .hw = &gxbb_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) static struct clk_regmap gxbb_hdmi_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .name = "hdmi_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .parent_data = gxbb_hdmi_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static struct clk_regmap gxbb_hdmi_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .name = "hdmi_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static struct clk_regmap gxbb_hdmi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .name = "hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) /* VDEC clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) static const struct clk_hw *gxbb_vdec_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) &gxbb_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) &gxbb_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) &gxbb_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) &gxbb_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) static struct clk_regmap gxbb_vdec_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .name = "vdec_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .parent_hws = gxbb_vdec_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) static struct clk_regmap gxbb_vdec_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .name = "vdec_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) &gxbb_vdec_1_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) static struct clk_regmap gxbb_vdec_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .name = "vdec_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) &gxbb_vdec_1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) static struct clk_regmap gxbb_vdec_hevc_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .name = "vdec_hevc_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .parent_hws = gxbb_vdec_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) static struct clk_regmap gxbb_vdec_hevc_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .name = "vdec_hevc_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) &gxbb_vdec_hevc_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) static struct clk_regmap gxbb_vdec_hevc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .name = "vdec_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) &gxbb_vdec_hevc_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) 9, 10, 11, 13, 14, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) static const struct clk_parent_data gen_clk_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) { .hw = &gxbb_vdec_1.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) { .hw = &gxbb_vdec_hevc.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) { .hw = &gxbb_mpll0.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) { .hw = &gxbb_mpll1.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) { .hw = &gxbb_mpll2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) { .hw = &gxbb_fclk_div4.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) { .hw = &gxbb_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) { .hw = &gxbb_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) { .hw = &gxbb_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) { .hw = &gxbb_gp0_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) static struct clk_regmap gxbb_gen_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .offset = HHI_GEN_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .table = mux_table_gen_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .name = "gen_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) * bits 15:12 selects from 14 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .parent_data = gen_clk_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .num_parents = ARRAY_SIZE(gen_clk_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) static struct clk_regmap gxbb_gen_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .offset = HHI_GEN_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .width = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .name = "gen_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) &gxbb_gen_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) static struct clk_regmap gxbb_gen_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) .offset = HHI_GEN_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .name = "gen_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) &gxbb_gen_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) #define MESON_GATE(_name, _reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) /* Everything Else (EE) domain gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) /* Always On (AO) domain gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) /* AIU gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) /* Array of all clocks provided by this provider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) [CLKID_CLK81] = &gxbb_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) [CLKID_MPLL0] = &gxbb_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) [CLKID_MPLL1] = &gxbb_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) [CLKID_MPLL2] = &gxbb_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) [CLKID_DDR] = &gxbb_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) [CLKID_DOS] = &gxbb_dos.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) [CLKID_ISA] = &gxbb_isa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) [CLKID_PL301] = &gxbb_pl301.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) [CLKID_PERIPHS] = &gxbb_periphs.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) [CLKID_SPICC] = &gxbb_spicc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) [CLKID_I2C] = &gxbb_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) [CLKID_RNG0] = &gxbb_rng0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) [CLKID_UART0] = &gxbb_uart0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) [CLKID_SDHC] = &gxbb_sdhc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) [CLKID_STREAM] = &gxbb_stream.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) [CLKID_SDIO] = &gxbb_sdio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) [CLKID_ABUF] = &gxbb_abuf.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) [CLKID_SPI] = &gxbb_spi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) [CLKID_ETH] = &gxbb_eth.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) [CLKID_DEMUX] = &gxbb_demux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) [CLKID_IEC958] = &gxbb_iec958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) [CLKID_AMCLK] = &gxbb_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) [CLKID_MIXER] = &gxbb_mixer.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) [CLKID_ADC] = &gxbb_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) [CLKID_BLKMV] = &gxbb_blkmv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) [CLKID_AIU] = &gxbb_aiu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) [CLKID_UART1] = &gxbb_uart1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) [CLKID_G2D] = &gxbb_g2d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) [CLKID_USB0] = &gxbb_usb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) [CLKID_USB1] = &gxbb_usb1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) [CLKID_RESET] = &gxbb_reset.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) [CLKID_NAND] = &gxbb_nand.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) [CLKID_USB] = &gxbb_usb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) [CLKID_VDIN1] = &gxbb_vdin1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) [CLKID_EFUSE] = &gxbb_efuse.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) [CLKID_DVIN] = &gxbb_dvin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) [CLKID_UART2] = &gxbb_uart2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) [CLKID_SANA] = &gxbb_sana.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) [CLKID_ENC480P] = &gxbb_enc480p.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) [CLKID_RNG1] = &gxbb_rng1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) [CLKID_EDP] = &gxbb_edp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) [CLKID_MALI_0] = &gxbb_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) [CLKID_MALI_1] = &gxbb_mali_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) [CLKID_MALI] = &gxbb_mali.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) [CLKID_VPU_0] = &gxbb_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) [CLKID_VPU_1] = &gxbb_vpu_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) [CLKID_VPU] = &gxbb_vpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) [CLKID_VAPB] = &gxbb_vapb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) [CLKID_VCLK] = &gxbb_vclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) [CLKID_VCLK2] = &gxbb_vclk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) [CLKID_HDMI] = &gxbb_hdmi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) [NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) .num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) static struct clk_hw_onecell_data gxl_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) [CLKID_CLK81] = &gxbb_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) [CLKID_MPLL0] = &gxbb_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) [CLKID_MPLL1] = &gxbb_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) [CLKID_MPLL2] = &gxbb_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) [CLKID_DDR] = &gxbb_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) [CLKID_DOS] = &gxbb_dos.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) [CLKID_ISA] = &gxbb_isa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) [CLKID_PL301] = &gxbb_pl301.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) [CLKID_PERIPHS] = &gxbb_periphs.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) [CLKID_SPICC] = &gxbb_spicc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) [CLKID_I2C] = &gxbb_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) [CLKID_RNG0] = &gxbb_rng0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) [CLKID_UART0] = &gxbb_uart0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) [CLKID_SDHC] = &gxbb_sdhc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) [CLKID_STREAM] = &gxbb_stream.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) [CLKID_SDIO] = &gxbb_sdio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) [CLKID_ABUF] = &gxbb_abuf.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) [CLKID_SPI] = &gxbb_spi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) [CLKID_ETH] = &gxbb_eth.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) [CLKID_DEMUX] = &gxbb_demux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) [CLKID_IEC958] = &gxbb_iec958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) [CLKID_AMCLK] = &gxbb_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) [CLKID_MIXER] = &gxbb_mixer.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) [CLKID_ADC] = &gxbb_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) [CLKID_BLKMV] = &gxbb_blkmv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) [CLKID_AIU] = &gxbb_aiu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) [CLKID_UART1] = &gxbb_uart1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) [CLKID_G2D] = &gxbb_g2d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) [CLKID_USB0] = &gxbb_usb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) [CLKID_USB1] = &gxbb_usb1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) [CLKID_RESET] = &gxbb_reset.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) [CLKID_NAND] = &gxbb_nand.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) [CLKID_USB] = &gxbb_usb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) [CLKID_VDIN1] = &gxbb_vdin1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) [CLKID_EFUSE] = &gxbb_efuse.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) [CLKID_DVIN] = &gxbb_dvin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) [CLKID_UART2] = &gxbb_uart2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) [CLKID_SANA] = &gxbb_sana.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) [CLKID_ENC480P] = &gxbb_enc480p.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) [CLKID_RNG1] = &gxbb_rng1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) [CLKID_EDP] = &gxbb_edp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) [CLKID_MALI_0] = &gxbb_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) [CLKID_MALI_1] = &gxbb_mali_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) [CLKID_MALI] = &gxbb_mali.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) [CLKID_VPU_0] = &gxbb_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) [CLKID_VPU_1] = &gxbb_vpu_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) [CLKID_VPU] = &gxbb_vpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) [CLKID_VAPB] = &gxbb_vapb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) [CLKID_VCLK] = &gxbb_vclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) [CLKID_VCLK2] = &gxbb_vclk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) [CLKID_HDMI] = &gxbb_hdmi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) [CLKID_ACODEC] = &gxl_acodec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) [NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) .num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) static struct clk_regmap *const gxbb_clk_regmaps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) &gxbb_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) &gxbb_ddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) &gxbb_dos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) &gxbb_isa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) &gxbb_pl301,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) &gxbb_periphs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) &gxbb_spicc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) &gxbb_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) &gxbb_sar_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) &gxbb_smart_card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) &gxbb_rng0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) &gxbb_uart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) &gxbb_sdhc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) &gxbb_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) &gxbb_async_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) &gxbb_sdio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) &gxbb_abuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) &gxbb_hiu_iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) &gxbb_assist_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) &gxbb_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) &gxbb_i2s_spdif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) &gxbb_eth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) &gxbb_demux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) &gxbb_aiu_glue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) &gxbb_iec958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) &gxbb_i2s_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) &gxbb_amclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) &gxbb_aififo2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) &gxbb_mixer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) &gxbb_mixer_iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) &gxbb_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) &gxbb_blkmv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) &gxbb_aiu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) &gxbb_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) &gxbb_g2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) &gxbb_usb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) &gxbb_usb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) &gxbb_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) &gxbb_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) &gxbb_dos_parser,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) &gxbb_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) &gxbb_vdin1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) &gxbb_ahb_arb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) &gxbb_efuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) &gxbb_boot_rom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) &gxbb_ahb_data_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) &gxbb_ahb_ctrl_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) &gxbb_hdmi_intr_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) &gxbb_hdmi_pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) &gxbb_usb1_ddr_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) &gxbb_usb0_ddr_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) &gxbb_mmc_pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) &gxbb_dvin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) &gxbb_uart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) &gxbb_sana,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) &gxbb_vpu_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) &gxbb_sec_ahb_ahb3_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) &gxbb_clk81_a53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) &gxbb_vclk2_venci0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) &gxbb_vclk2_venci1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) &gxbb_vclk2_vencp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) &gxbb_vclk2_vencp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) &gxbb_gclk_venci_int0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) &gxbb_gclk_vencp_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) &gxbb_dac_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) &gxbb_aoclk_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) &gxbb_iec958_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) &gxbb_enc480p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) &gxbb_rng1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) &gxbb_gclk_venci_int1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) &gxbb_vclk2_venclmcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) &gxbb_vclk2_vencl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) &gxbb_vclk_other,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) &gxbb_edp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) &gxbb_ao_media_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) &gxbb_ao_ahb_sram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) &gxbb_ao_ahb_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) &gxbb_ao_iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) &gxbb_ao_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) &gxbb_emmc_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) &gxbb_emmc_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) &gxbb_emmc_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) &gxbb_sar_adc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) &gxbb_mali_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) &gxbb_mali_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) &gxbb_cts_amclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) &gxbb_cts_mclk_i958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) &gxbb_32k_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) &gxbb_sd_emmc_a_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) &gxbb_sd_emmc_b_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) &gxbb_sd_emmc_c_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) &gxbb_vpu_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) &gxbb_vpu_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) &gxbb_vapb_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) &gxbb_vapb_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) &gxbb_vapb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) &gxbb_mpeg_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) &gxbb_sar_adc_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) &gxbb_mali_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) &gxbb_mali_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) &gxbb_cts_mclk_i958_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) &gxbb_32k_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) &gxbb_sd_emmc_a_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) &gxbb_sd_emmc_b_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) &gxbb_sd_emmc_c_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) &gxbb_vpu_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) &gxbb_vpu_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) &gxbb_vapb_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) &gxbb_vapb_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) &gxbb_mpeg_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) &gxbb_sar_adc_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) &gxbb_mali_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) &gxbb_mali_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) &gxbb_mali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) &gxbb_cts_amclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) &gxbb_cts_mclk_i958_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) &gxbb_cts_i958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) &gxbb_32k_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) &gxbb_sd_emmc_a_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) &gxbb_sd_emmc_b_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) &gxbb_sd_emmc_c_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) &gxbb_vpu_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) &gxbb_vpu_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) &gxbb_vpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) &gxbb_vapb_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) &gxbb_vapb_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) &gxbb_vapb_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) &gxbb_mpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) &gxbb_mpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) &gxbb_mpll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) &gxbb_mpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) &gxbb_mpll1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) &gxbb_mpll2_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) &gxbb_cts_amclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) &gxbb_fixed_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) &gxbb_sys_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) &gxbb_mpll_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) &gxbb_fclk_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) &gxbb_fclk_div3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) &gxbb_fclk_div4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) &gxbb_fclk_div5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) &gxbb_fclk_div7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) &gxbb_vdec_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) &gxbb_vdec_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) &gxbb_vdec_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) &gxbb_vdec_hevc_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) &gxbb_vdec_hevc_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) &gxbb_vdec_hevc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) &gxbb_gen_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) &gxbb_gen_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) &gxbb_gen_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) &gxbb_fixed_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) &gxbb_sys_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) &gxbb_gp0_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) &gxbb_vid_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) &gxbb_vid_pll_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) &gxbb_vid_pll_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) &gxbb_vclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) &gxbb_vclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) &gxbb_vclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) &gxbb_vclk_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) &gxbb_vclk_div1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) &gxbb_vclk_div2_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) &gxbb_vclk_div4_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) &gxbb_vclk_div6_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) &gxbb_vclk_div12_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) &gxbb_vclk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) &gxbb_vclk2_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) &gxbb_vclk2_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) &gxbb_vclk2_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) &gxbb_vclk2_div1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) &gxbb_vclk2_div2_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) &gxbb_vclk2_div4_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) &gxbb_vclk2_div6_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) &gxbb_vclk2_div12_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) &gxbb_cts_enci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) &gxbb_cts_enci_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) &gxbb_cts_encp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) &gxbb_cts_encp_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) &gxbb_cts_vdac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) &gxbb_cts_vdac_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) &gxbb_hdmi_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) &gxbb_hdmi_tx_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) &gxbb_hdmi_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) &gxbb_hdmi_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) &gxbb_hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) &gxbb_gp0_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) &gxbb_hdmi_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) &gxbb_hdmi_pll_od,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) &gxbb_hdmi_pll_od2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) &gxbb_hdmi_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) static struct clk_regmap *const gxl_clk_regmaps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) &gxbb_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) &gxbb_ddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) &gxbb_dos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) &gxbb_isa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) &gxbb_pl301,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) &gxbb_periphs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) &gxbb_spicc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) &gxbb_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) &gxbb_sar_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) &gxbb_smart_card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) &gxbb_rng0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) &gxbb_uart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) &gxbb_sdhc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) &gxbb_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) &gxbb_async_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) &gxbb_sdio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) &gxbb_abuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) &gxbb_hiu_iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) &gxbb_assist_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) &gxbb_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) &gxbb_i2s_spdif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) &gxbb_eth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) &gxbb_demux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) &gxbb_aiu_glue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) &gxbb_iec958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) &gxbb_i2s_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) &gxbb_amclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) &gxbb_aififo2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) &gxbb_mixer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) &gxbb_mixer_iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) &gxbb_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) &gxbb_blkmv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) &gxbb_aiu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) &gxbb_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) &gxbb_g2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) &gxbb_usb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) &gxbb_usb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) &gxbb_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) &gxbb_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) &gxbb_dos_parser,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) &gxbb_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) &gxbb_vdin1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) &gxbb_ahb_arb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) &gxbb_efuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) &gxbb_boot_rom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) &gxbb_ahb_data_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) &gxbb_ahb_ctrl_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) &gxbb_hdmi_intr_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) &gxbb_hdmi_pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) &gxbb_usb1_ddr_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) &gxbb_usb0_ddr_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) &gxbb_mmc_pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) &gxbb_dvin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) &gxbb_uart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) &gxbb_sana,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) &gxbb_vpu_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) &gxbb_sec_ahb_ahb3_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) &gxbb_clk81_a53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) &gxbb_vclk2_venci0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) &gxbb_vclk2_venci1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) &gxbb_vclk2_vencp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) &gxbb_vclk2_vencp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) &gxbb_gclk_venci_int0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) &gxbb_gclk_vencp_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) &gxbb_dac_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) &gxbb_aoclk_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) &gxbb_iec958_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) &gxbb_enc480p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) &gxbb_rng1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) &gxbb_gclk_venci_int1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) &gxbb_vclk2_venclmcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) &gxbb_vclk2_vencl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) &gxbb_vclk_other,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) &gxbb_edp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) &gxbb_ao_media_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) &gxbb_ao_ahb_sram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) &gxbb_ao_ahb_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) &gxbb_ao_iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) &gxbb_ao_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) &gxbb_emmc_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) &gxbb_emmc_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) &gxbb_emmc_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) &gxbb_sar_adc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) &gxbb_mali_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) &gxbb_mali_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) &gxbb_cts_amclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) &gxbb_cts_mclk_i958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) &gxbb_32k_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) &gxbb_sd_emmc_a_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) &gxbb_sd_emmc_b_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) &gxbb_sd_emmc_c_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) &gxbb_vpu_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) &gxbb_vpu_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) &gxbb_vapb_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) &gxbb_vapb_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) &gxbb_vapb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) &gxbb_mpeg_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) &gxbb_sar_adc_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) &gxbb_mali_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) &gxbb_mali_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) &gxbb_cts_mclk_i958_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) &gxbb_32k_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) &gxbb_sd_emmc_a_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) &gxbb_sd_emmc_b_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) &gxbb_sd_emmc_c_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) &gxbb_vpu_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) &gxbb_vpu_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) &gxbb_vapb_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) &gxbb_vapb_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) &gxbb_mpeg_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) &gxbb_sar_adc_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) &gxbb_mali_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) &gxbb_mali_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) &gxbb_mali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) &gxbb_cts_amclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) &gxbb_cts_mclk_i958_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) &gxbb_cts_i958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) &gxbb_32k_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) &gxbb_sd_emmc_a_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) &gxbb_sd_emmc_b_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) &gxbb_sd_emmc_c_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) &gxbb_vpu_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) &gxbb_vpu_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) &gxbb_vpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) &gxbb_vapb_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) &gxbb_vapb_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) &gxbb_vapb_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) &gxbb_mpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) &gxbb_mpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) &gxbb_mpll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) &gxl_mpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) &gxbb_mpll1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) &gxbb_mpll2_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) &gxbb_cts_amclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) &gxbb_fixed_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) &gxbb_sys_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) &gxbb_mpll_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) &gxbb_fclk_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) &gxbb_fclk_div3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) &gxbb_fclk_div4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) &gxbb_fclk_div5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) &gxbb_fclk_div7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) &gxbb_vdec_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) &gxbb_vdec_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) &gxbb_vdec_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) &gxbb_vdec_hevc_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) &gxbb_vdec_hevc_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) &gxbb_vdec_hevc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) &gxbb_gen_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) &gxbb_gen_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) &gxbb_gen_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) &gxbb_fixed_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) &gxbb_sys_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) &gxbb_gp0_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) &gxbb_vid_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) &gxbb_vid_pll_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) &gxbb_vid_pll_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) &gxbb_vclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) &gxbb_vclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) &gxbb_vclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) &gxbb_vclk_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) &gxbb_vclk_div1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) &gxbb_vclk_div2_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) &gxbb_vclk_div4_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) &gxbb_vclk_div6_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) &gxbb_vclk_div12_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) &gxbb_vclk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) &gxbb_vclk2_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) &gxbb_vclk2_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) &gxbb_vclk2_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) &gxbb_vclk2_div1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) &gxbb_vclk2_div2_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) &gxbb_vclk2_div4_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) &gxbb_vclk2_div6_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) &gxbb_vclk2_div12_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) &gxbb_cts_enci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) &gxbb_cts_enci_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) &gxbb_cts_encp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) &gxbb_cts_encp_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) &gxbb_cts_vdac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) &gxbb_cts_vdac_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) &gxbb_hdmi_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) &gxbb_hdmi_tx_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) &gxbb_hdmi_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) &gxbb_hdmi_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) &gxbb_hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) &gxl_gp0_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) &gxl_hdmi_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) &gxl_hdmi_pll_od,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) &gxl_hdmi_pll_od2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) &gxl_hdmi_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) &gxl_acodec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) static const struct meson_eeclkc_data gxbb_clkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) .regmap_clks = gxbb_clk_regmaps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) .hw_onecell_data = &gxbb_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) static const struct meson_eeclkc_data gxl_clkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) .regmap_clks = gxl_clk_regmaps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) .hw_onecell_data = &gxl_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) static const struct of_device_id clkc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) MODULE_DEVICE_TABLE(of, clkc_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) static struct platform_driver gxbb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) .probe = meson_eeclkc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) .name = "gxbb-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) .of_match_table = clkc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) module_platform_driver(gxbb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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