^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "meson-aoclk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "gxbb-aoclk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-dualdiv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* AO Configuration Clock registers offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AO_RTI_PWR_CNTL_REG1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AO_RTI_PWR_CNTL_REG0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AO_RTI_GEN_CNTL_REG0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AO_OSCIN_CNTL 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AO_CRT_CLK_CNTL1 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AO_RTC_ALT_CLK_CNTL0 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AO_RTC_ALT_CLK_CNTL1 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GXBB_AO_GATE(_name, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct clk_regmap _name##_ao = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .data = &(struct clk_regmap_gate_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .offset = AO_RTI_GEN_CNTL_REG0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .bit_idx = (_bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .name = #_name "_ao", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .ops = &clk_regmap_gate_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .parent_data = &(const struct clk_parent_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .fw_name = "mpeg-clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .flags = CLK_IGNORE_UNUSED, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) GXBB_AO_GATE(remote, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) GXBB_AO_GATE(i2c_master, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) GXBB_AO_GATE(i2c_slave, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) GXBB_AO_GATE(uart1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GXBB_AO_GATE(uart2, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) GXBB_AO_GATE(ir_blaster, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct clk_regmap ao_cts_oscin = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .offset = AO_RTI_PWR_CNTL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .bit_idx = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = "ao_cts_oscin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct clk_regmap ao_32k_pre = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .offset = AO_RTC_ALT_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .bit_idx = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .name = "ao_32k_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct meson_clk_dualdiv_param gxbb_32k_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .dual = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .n1 = 733,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .m1 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .n2 = 732,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .m2 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }, {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct clk_regmap ao_32k_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .data = &(struct meson_clk_dualdiv_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .n1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .reg_off = AO_RTC_ALT_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .reg_off = AO_RTC_ALT_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .m1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .reg_off = AO_RTC_ALT_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .m2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .reg_off = AO_RTC_ALT_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .dual = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .reg_off = AO_RTC_ALT_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .table = gxbb_32k_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .name = "ao_32k_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .ops = &meson_clk_dualdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct clk_regmap ao_32k_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .data = &(struct clk_regmap_mux_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .offset = AO_RTC_ALT_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "ao_32k_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) &ao_32k_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) &ao_32k_pre.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct clk_regmap ao_32k = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .offset = AO_RTC_ALT_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .bit_idx = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "ao_32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct clk_regmap ao_cts_rtc_oscin = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .data = &(struct clk_regmap_mux_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .offset = AO_RTI_PWR_CNTL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .table = (u32[]){ 1, 2, 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "ao_cts_rtc_oscin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .fw_name = "ext-32k-0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .fw_name = "ext-32k-1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .fw_name = "ext-32k-2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .hw = &ao_32k.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct clk_regmap ao_clk81 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .data = &(struct clk_regmap_mux_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .offset = AO_RTI_PWR_CNTL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .name = "ao_clk81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .fw_name = "mpeg-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .hw = &ao_cts_rtc_oscin.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct clk_regmap ao_cts_cec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .data = &(struct clk_regmap_mux_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .offset = AO_CRT_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .shift = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .name = "ao_cts_cec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * FIXME: The 'fixme' parent obviously does not exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * ATM, CCF won't call get_parent() if num_parents is 1. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * does not allow NULL as a parent name either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * On this particular mux, we only know the input #1 parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * but, on boot, unknown input #0 is set, so it is critical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * to call .get_parent() on it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Until CCF gets fixed, adding this fake parent that won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * ever be registered should work around the problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { .name = "fixme", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { .hw = &ao_cts_rtc_oscin.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const unsigned int gxbb_aoclk_reset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [RESET_AO_REMOTE] = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [RESET_AO_I2C_MASTER] = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [RESET_AO_I2C_SLAVE] = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [RESET_AO_UART1] = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [RESET_AO_UART2] = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [RESET_AO_IR_BLASTER] = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct clk_regmap *gxbb_aoclk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) &remote_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) &i2c_master_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) &i2c_slave_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) &uart1_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) &uart2_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) &ir_blaster_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) &ao_cts_oscin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) &ao_32k_pre,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) &ao_32k_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) &ao_32k_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) &ao_32k,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) &ao_cts_rtc_oscin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) &ao_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) &ao_cts_cec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [CLKID_AO_REMOTE] = &remote_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [CLKID_AO_UART1] = &uart1_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [CLKID_AO_UART2] = &uart2_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [CLKID_AO_CEC_32K] = &ao_cts_cec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [CLKID_AO_CTS_OSCIN] = &ao_cts_oscin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [CLKID_AO_32K_PRE] = &ao_32k_pre.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) [CLKID_AO_32K_DIV] = &ao_32k_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) [CLKID_AO_32K_SEL] = &ao_32k_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) [CLKID_AO_32K] = &ao_32k.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [CLKID_AO_CLK81] = &ao_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct meson_aoclk_data gxbb_aoclkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .reset_reg = AO_RTI_GEN_CNTL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .reset = gxbb_aoclk_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .num_clks = ARRAY_SIZE(gxbb_aoclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .clks = gxbb_aoclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .hw_data = &gxbb_aoclk_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct of_device_id gxbb_aoclkc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .compatible = "amlogic,meson-gx-aoclkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .data = &gxbb_aoclkc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_DEVICE_TABLE(of, gxbb_aoclkc_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct platform_driver gxbb_aoclkc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .probe = meson_aoclkc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "gxbb-aoclkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .of_match_table = gxbb_aoclkc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) module_platform_driver(gxbb_aoclkc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags