Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2016 Amlogic, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Michael Turquette <mturquette@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2018 Amlogic, inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Jian Hu <jian.hu@amlogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef __G12A_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define __G12A_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Clock controller register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Register offsets from the data sheet must be multiplied by 4 before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * adding them to the base address to get the right value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define HHI_MIPI_CNTL0			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define HHI_MIPI_CNTL1			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define HHI_MIPI_CNTL2			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define HHI_MIPI_STS			0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define HHI_GP0_PLL_CNTL0		0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define HHI_GP0_PLL_CNTL1		0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define HHI_GP0_PLL_CNTL2		0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define HHI_GP0_PLL_CNTL3		0x04C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define HHI_GP0_PLL_CNTL4		0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HHI_GP0_PLL_CNTL5		0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define HHI_GP0_PLL_CNTL6		0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HHI_GP0_PLL_STS			0x05C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define HHI_GP1_PLL_CNTL0		0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define HHI_GP1_PLL_CNTL1		0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define HHI_GP1_PLL_CNTL2		0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define HHI_GP1_PLL_CNTL3		0x06C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define HHI_GP1_PLL_CNTL4		0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define HHI_GP1_PLL_CNTL5		0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define HHI_GP1_PLL_CNTL6		0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define HHI_GP1_PLL_STS			0x07C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define HHI_PCIE_PLL_CNTL0		0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define HHI_PCIE_PLL_CNTL1		0x09C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define HHI_PCIE_PLL_CNTL2		0x0A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define HHI_PCIE_PLL_CNTL3		0x0A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define HHI_PCIE_PLL_CNTL4		0x0A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define HHI_PCIE_PLL_CNTL5		0x0AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define HHI_PCIE_PLL_STS		0x0B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define HHI_HIFI_PLL_CNTL0		0x0D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define HHI_HIFI_PLL_CNTL1		0x0DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define HHI_HIFI_PLL_CNTL2		0x0E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define HHI_HIFI_PLL_CNTL3		0x0E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define HHI_HIFI_PLL_CNTL4		0x0E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define HHI_HIFI_PLL_CNTL5		0x0EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define HHI_HIFI_PLL_CNTL6		0x0F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define HHI_VIID_CLK_DIV		0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define HHI_VIID_CLK_CNTL		0x12C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define HHI_GCLK_MPEG0			0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define HHI_GCLK_MPEG1			0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define HHI_GCLK_MPEG2			0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define HHI_GCLK_OTHER			0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define HHI_GCLK_OTHER2			0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define HHI_SYS_CPU_CLK_CNTL1		0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define HHI_VID_CLK_DIV			0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define HHI_MPEG_CLK_CNTL		0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define HHI_AUD_CLK_CNTL		0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define HHI_VID_CLK_CNTL		0x17c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define HHI_TS_CLK_CNTL			0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define HHI_VID_CLK_CNTL2		0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define HHI_SYS_CPU_CLK_CNTL0		0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define HHI_VID_PLL_CLK_DIV		0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define HHI_MALI_CLK_CNTL		0x1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define HHI_VPU_CLKC_CNTL		0x1b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define HHI_VPU_CLK_CNTL		0x1bC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define HHI_NNA_CLK_CNTL		0x1C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define HHI_HDMI_CLK_CNTL		0x1CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define HHI_VDEC_CLK_CNTL		0x1E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define HHI_VDEC2_CLK_CNTL		0x1E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define HHI_VDEC3_CLK_CNTL		0x1E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define HHI_VDEC4_CLK_CNTL		0x1EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define HHI_HDCP22_CLK_CNTL		0x1F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define HHI_VAPBCLK_CNTL		0x1F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define HHI_SYS_CPUB_CLK_CNTL1		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define HHI_SYS_CPUB_CLK_CNTL		0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define HHI_VPU_CLKB_CNTL		0x20C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define HHI_SYS_CPU_CLK_CNTL2		0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define HHI_SYS_CPU_CLK_CNTL3		0x214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define HHI_SYS_CPU_CLK_CNTL4		0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define HHI_SYS_CPU_CLK_CNTL5		0x21c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define HHI_SYS_CPU_CLK_CNTL6		0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define HHI_GEN_CLK_CNTL		0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define HHI_VDIN_MEAS_CLK_CNTL		0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define HHI_MIPIDSI_PHY_CLK_CNTL	0x254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define HHI_NAND_CLK_CNTL		0x25C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define HHI_SD_EMMC_CLK_CNTL		0x264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define HHI_MPLL_CNTL0			0x278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define HHI_MPLL_CNTL1			0x27C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define HHI_MPLL_CNTL2			0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define HHI_MPLL_CNTL3			0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define HHI_MPLL_CNTL4			0x288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define HHI_MPLL_CNTL5			0x28c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HHI_MPLL_CNTL6			0x290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HHI_MPLL_CNTL7			0x294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HHI_MPLL_CNTL8			0x298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HHI_FIX_PLL_CNTL0		0x2A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HHI_FIX_PLL_CNTL1		0x2A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HHI_FIX_PLL_CNTL3		0x2AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HHI_SYS_PLL_CNTL0		0x2f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HHI_SYS_PLL_CNTL1		0x2f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HHI_SYS_PLL_CNTL2		0x2fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HHI_SYS_PLL_CNTL3		0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HHI_SYS_PLL_CNTL4		0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HHI_SYS_PLL_CNTL5		0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HHI_SYS_PLL_CNTL6		0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HHI_HDMI_PLL_CNTL0		0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HHI_HDMI_PLL_CNTL1		0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HHI_HDMI_PLL_CNTL2		0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HHI_HDMI_PLL_CNTL3		0x32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HHI_HDMI_PLL_CNTL4		0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HHI_HDMI_PLL_CNTL5		0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HHI_HDMI_PLL_CNTL6		0x338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HHI_SPICC_CLK_CNTL		0x3dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HHI_SYS1_PLL_CNTL0		0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HHI_SYS1_PLL_CNTL1		0x384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HHI_SYS1_PLL_CNTL2		0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HHI_SYS1_PLL_CNTL3		0x38c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HHI_SYS1_PLL_CNTL4		0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HHI_SYS1_PLL_CNTL5		0x394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HHI_SYS1_PLL_CNTL6		0x398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * CLKID index values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * These indices are entirely contrived and do not map onto the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * It has now been decided to expose everything by default in the DT header:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * to expose, such as the internal muxes and dividers of composite clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * will remain defined here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLKID_MPEG_SEL				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLKID_MPEG_DIV				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLKID_SD_EMMC_A_CLK0_SEL		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLKID_SD_EMMC_A_CLK0_DIV		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLKID_SD_EMMC_B_CLK0_SEL		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLKID_SD_EMMC_B_CLK0_DIV		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLKID_SD_EMMC_C_CLK0_SEL		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLKID_SD_EMMC_C_CLK0_DIV		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLKID_MPLL0_DIV				69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLKID_MPLL1_DIV				70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLKID_MPLL2_DIV				71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLKID_MPLL3_DIV				72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLKID_MPLL_PREDIV			73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLKID_FCLK_DIV2_DIV			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLKID_FCLK_DIV3_DIV			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLKID_FCLK_DIV4_DIV			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLKID_FCLK_DIV5_DIV			78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLKID_FCLK_DIV7_DIV			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLKID_FCLK_DIV2P5_DIV			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLKID_FIXED_PLL_DCO			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLKID_SYS_PLL_DCO			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLKID_GP0_PLL_DCO			103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLKID_HIFI_PLL_DCO			104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLKID_VPU_0_DIV				111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLKID_VPU_1_DIV				114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLKID_VAPB_0_DIV			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLKID_VAPB_1_DIV			121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLKID_HDMI_PLL_DCO			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLKID_HDMI_PLL_OD			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLKID_HDMI_PLL_OD2			127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLKID_VID_PLL_SEL			130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLKID_VID_PLL_DIV			131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLKID_VCLK_SEL				132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLKID_VCLK2_SEL				133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLKID_VCLK_INPUT			134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLKID_VCLK2_INPUT			135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLKID_VCLK_DIV				136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLKID_VCLK2_DIV				137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLKID_VCLK_DIV2_EN			140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLKID_VCLK_DIV4_EN			141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLKID_VCLK_DIV6_EN			142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLKID_VCLK_DIV12_EN			143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLKID_VCLK2_DIV2_EN			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLKID_VCLK2_DIV4_EN			145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLKID_VCLK2_DIV6_EN			146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLKID_VCLK2_DIV12_EN			147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLKID_CTS_ENCI_SEL			158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLKID_CTS_ENCP_SEL			159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLKID_CTS_VDAC_SEL			160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLKID_HDMI_TX_SEL			161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLKID_HDMI_SEL				166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLKID_HDMI_DIV				167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLKID_MALI_0_DIV			170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLKID_MALI_1_DIV			173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLKID_MPLL_50M_DIV			176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLKID_SYS_PLL_DIV16_EN			178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLKID_SYS_PLL_DIV16			179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLKID_CPU_CLK_DYN0_SEL			180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLKID_CPU_CLK_DYN0_DIV			181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLKID_CPU_CLK_DYN0			182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLKID_CPU_CLK_DYN1_SEL			183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLKID_CPU_CLK_DYN1_DIV			184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLKID_CPU_CLK_DYN1			185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLKID_CPU_CLK_DYN			186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLKID_CPU_CLK_DIV16_EN			188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLKID_CPU_CLK_DIV16			189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLKID_CPU_CLK_APB_DIV			190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLKID_CPU_CLK_APB			191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLKID_CPU_CLK_ATB_DIV			192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLKID_CPU_CLK_ATB			193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLKID_CPU_CLK_AXI_DIV			194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLKID_CPU_CLK_AXI			195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLKID_CPU_CLK_TRACE_DIV			196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLKID_CPU_CLK_TRACE			197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLKID_PCIE_PLL_DCO			198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLKID_PCIE_PLL_DCO_DIV2			199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLKID_PCIE_PLL_OD			200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLKID_VDEC_1_SEL			202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLKID_VDEC_1_DIV			203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLKID_VDEC_HEVC_SEL			205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLKID_VDEC_HEVC_DIV			206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLKID_VDEC_HEVCF_SEL			208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLKID_VDEC_HEVCF_DIV			209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLKID_TS_DIV				211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLKID_SYS1_PLL_DCO			213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLKID_SYS1_PLL				214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLKID_SYS1_PLL_DIV16_EN			215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLKID_SYS1_PLL_DIV16			216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLKID_CPUB_CLK_DYN0_SEL			217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLKID_CPUB_CLK_DYN0_DIV			218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLKID_CPUB_CLK_DYN0			219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLKID_CPUB_CLK_DYN1_SEL			220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLKID_CPUB_CLK_DYN1_DIV			221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLKID_CPUB_CLK_DYN1			222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLKID_CPUB_CLK_DYN			223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLKID_CPUB_CLK_DIV16_EN			225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLKID_CPUB_CLK_DIV16			226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLKID_CPUB_CLK_DIV2			227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLKID_CPUB_CLK_DIV3			228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLKID_CPUB_CLK_DIV4			229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLKID_CPUB_CLK_DIV5			230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLKID_CPUB_CLK_DIV6			231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLKID_CPUB_CLK_DIV7			232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLKID_CPUB_CLK_DIV8			233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLKID_CPUB_CLK_APB_SEL			234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLKID_CPUB_CLK_APB			235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLKID_CPUB_CLK_ATB_SEL			236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLKID_CPUB_CLK_ATB			237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLKID_CPUB_CLK_AXI_SEL			238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLKID_CPUB_CLK_AXI			239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLKID_CPUB_CLK_TRACE_SEL		240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLKID_CPUB_CLK_TRACE			241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLKID_GP1_PLL_DCO			242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLKID_DSU_CLK_DYN0_SEL			244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLKID_DSU_CLK_DYN0_DIV			245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLKID_DSU_CLK_DYN0			246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CLKID_DSU_CLK_DYN1_SEL			247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLKID_DSU_CLK_DYN1_DIV			248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLKID_DSU_CLK_DYN1			249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLKID_DSU_CLK_DYN			250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLKID_DSU_CLK_FINAL			251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLKID_SPICC0_SCLK_SEL			256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLKID_SPICC0_SCLK_DIV			257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLKID_SPICC1_SCLK_SEL			259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLKID_SPICC1_SCLK_DIV			260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLKID_NNA_AXI_CLK_SEL			262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLKID_NNA_AXI_CLK_DIV			263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLKID_NNA_CORE_CLK_SEL			265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLKID_NNA_CORE_CLK_DIV			266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define NR_CLKS					268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* include the CLKIDs that have been made part of the DT binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #include <dt-bindings/clock/g12a-clkc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #endif /* __G12A_H */