^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Amlogic Meson-G12A Clock Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Baylibre SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Michael Turquette <mturquette@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2018 Amlogic, inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Qiufang Dai <qiufang.dai@amlogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Jian Hu <jian.hu@amlogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-mpll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-cpu-dyndiv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "vid-pll-div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "meson-eeclk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "g12a.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static DEFINE_SPINLOCK(meson_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct clk_regmap g12a_fixed_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .reg_off = HHI_FIX_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .reg_off = HHI_FIX_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .reg_off = HHI_FIX_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .reg_off = HHI_FIX_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .width = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .reg_off = HHI_FIX_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .reg_off = HHI_FIX_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .name = "fixed_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct clk_regmap g12a_fixed_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .offset = HHI_FIX_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .name = "fixed_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) &g12a_fixed_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * This clock won't ever change at runtime so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * CLK_SET_RATE_PARENT is not required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct pll_mult_range g12a_sys_pll_mult_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .min = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .max = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct clk_regmap g12a_sys_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .reg_off = HHI_SYS_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .reg_off = HHI_SYS_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .reg_off = HHI_SYS_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .reg_off = HHI_SYS_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reg_off = HHI_SYS_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .range = &g12a_sys_pll_mult_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "sys_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* This clock feeds the CPU, avoid disabling it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct clk_regmap g12a_sys_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .offset = HHI_SYS_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "sys_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) &g12a_sys_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct clk_regmap g12b_sys1_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .reg_off = HHI_SYS1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .reg_off = HHI_SYS1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .reg_off = HHI_SYS1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .reg_off = HHI_SYS1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .reg_off = HHI_SYS1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .range = &g12a_sys_pll_mult_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "sys1_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* This clock feeds the CPU, avoid disabling it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct clk_regmap g12b_sys1_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .offset = HHI_SYS1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .name = "sys1_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) &g12b_sys1_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct clk_regmap g12a_sys_pll_div16_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .name = "sys_pll_div16_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * This clock is used to debug the sys_pll range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct clk_regmap g12b_sys1_pll_div16_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .offset = HHI_SYS_CPUB_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .name = "sys1_pll_div16_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) &g12b_sys1_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * This clock is used to debug the sys_pll range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct clk_fixed_factor g12a_sys_pll_div16 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .div = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .name = "sys_pll_div16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) &g12a_sys_pll_div16_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct clk_fixed_factor g12b_sys1_pll_div16 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .div = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .name = "sys1_pll_div16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) &g12b_sys1_pll_div16_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct clk_fixed_factor g12a_fclk_div2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "fclk_div2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static struct clk_regmap g12a_fclk_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .offset = HHI_FIX_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "fclk_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) &g12a_fclk_div2_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Similar to fclk_div3, it seems that this clock is used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * the resident firmware and is required by the platform to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * operate correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Until the following condition are met, we need this clock to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * be marked as critical:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * a) Mark the clock used by a firmware resource, if possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * b) CCF has a clock hand-off mechanism to make the sure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * clock stays on until the proper driver comes along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct clk_fixed_factor g12a_fclk_div3_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .div = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .name = "fclk_div3_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct clk_regmap g12a_fclk_div3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .offset = HHI_FIX_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .bit_idx = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = "fclk_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) &g12a_fclk_div3_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * This clock is used by the resident firmware and is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * by the platform to operate correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Until the following condition are met, we need this clock to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * be marked as critical:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * a) Mark the clock used by a firmware resource, if possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * b) CCF has a clock hand-off mechanism to make the sure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * clock stays on until the proper driver comes along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Datasheet names this field as "premux0" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct clk_regmap g12a_cpu_clk_premux0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .name = "cpu_clk_dyn0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { .hw = &g12a_fclk_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Datasheet names this field as "premux1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct clk_regmap g12a_cpu_clk_premux1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .name = "cpu_clk_dyn1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { .hw = &g12a_fclk_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* This sub-tree is used a parking clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .flags = CLK_SET_RATE_NO_REPARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Datasheet names this field as "mux0_divn_tcnt" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct clk_regmap g12a_cpu_clk_mux0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .data = &(struct meson_clk_cpu_dyndiv_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .reg_off = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .width = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .dyn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .reg_off = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .shift = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .name = "cpu_clk_dyn0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .ops = &meson_clk_cpu_dyndiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) &g12a_cpu_clk_premux0.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Datasheet names this field as "postmux0" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static struct clk_regmap g12a_cpu_clk_postmux0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .name = "cpu_clk_dyn0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) &g12a_cpu_clk_premux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) &g12a_cpu_clk_mux0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Datasheet names this field as "Mux1_divn_tcnt" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct clk_regmap g12a_cpu_clk_mux1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .width = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .name = "cpu_clk_dyn1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) &g12a_cpu_clk_premux1.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Datasheet names this field as "postmux1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static struct clk_regmap g12a_cpu_clk_postmux1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .name = "cpu_clk_dyn1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) &g12a_cpu_clk_premux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) &g12a_cpu_clk_mux1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* This sub-tree is used a parking clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Datasheet names this field as "Final_dyn_mux_sel" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static struct clk_regmap g12a_cpu_clk_dyn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .name = "cpu_clk_dyn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &g12a_cpu_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) &g12a_cpu_clk_postmux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Datasheet names this field as "Final_mux_sel" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static struct clk_regmap g12a_cpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .name = "cpu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) &g12a_cpu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) &g12a_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Datasheet names this field as "Final_mux_sel" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static struct clk_regmap g12b_cpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .offset = HHI_SYS_CPU_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .name = "cpu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &g12a_cpu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &g12b_sys1_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Datasheet names this field as "premux0" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct clk_regmap g12b_cpub_clk_premux0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .offset = HHI_SYS_CPUB_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .name = "cpub_clk_dyn0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { .hw = &g12a_fclk_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Datasheet names this field as "mux0_divn_tcnt" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct clk_regmap g12b_cpub_clk_mux0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .data = &(struct meson_clk_cpu_dyndiv_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .reg_off = HHI_SYS_CPUB_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .width = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .dyn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .reg_off = HHI_SYS_CPUB_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .shift = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .name = "cpub_clk_dyn0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .ops = &meson_clk_cpu_dyndiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) &g12b_cpub_clk_premux0.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Datasheet names this field as "postmux0" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static struct clk_regmap g12b_cpub_clk_postmux0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .offset = HHI_SYS_CPUB_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .name = "cpub_clk_dyn0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) &g12b_cpub_clk_premux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) &g12b_cpub_clk_mux0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Datasheet names this field as "premux1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static struct clk_regmap g12b_cpub_clk_premux1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .offset = HHI_SYS_CPUB_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .name = "cpub_clk_dyn1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { .hw = &g12a_fclk_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* This sub-tree is used a parking clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Datasheet names this field as "Mux1_divn_tcnt" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static struct clk_regmap g12b_cpub_clk_mux1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .offset = HHI_SYS_CPUB_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .width = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .name = "cpub_clk_dyn1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) &g12b_cpub_clk_premux1.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Datasheet names this field as "postmux1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static struct clk_regmap g12b_cpub_clk_postmux1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .offset = HHI_SYS_CPUB_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .name = "cpub_clk_dyn1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) &g12b_cpub_clk_premux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) &g12b_cpub_clk_mux1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* This sub-tree is used a parking clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Datasheet names this field as "Final_dyn_mux_sel" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static struct clk_regmap g12b_cpub_clk_dyn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .offset = HHI_SYS_CPUB_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .name = "cpub_clk_dyn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) &g12b_cpub_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) &g12b_cpub_clk_postmux1.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Datasheet names this field as "Final_mux_sel" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static struct clk_regmap g12b_cpub_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .offset = HHI_SYS_CPUB_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .name = "cpub_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) &g12b_cpub_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) &g12a_sys_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static struct clk_regmap sm1_gp1_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Datasheet names this field as "premux0" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct clk_regmap sm1_dsu_clk_premux0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .offset = HHI_SYS_CPU_CLK_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .name = "dsu_clk_dyn0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) { .hw = &g12a_fclk_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) { .hw = &sm1_gp1_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Datasheet names this field as "premux1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static struct clk_regmap sm1_dsu_clk_premux1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .offset = HHI_SYS_CPU_CLK_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .name = "dsu_clk_dyn1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) { .hw = &g12a_fclk_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { .hw = &sm1_gp1_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* Datasheet names this field as "Mux0_divn_tcnt" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static struct clk_regmap sm1_dsu_clk_mux0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .offset = HHI_SYS_CPU_CLK_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .width = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .name = "dsu_clk_dyn0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) &sm1_dsu_clk_premux0.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Datasheet names this field as "postmux0" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static struct clk_regmap sm1_dsu_clk_postmux0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .offset = HHI_SYS_CPU_CLK_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .name = "dsu_clk_dyn0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) &sm1_dsu_clk_premux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) &sm1_dsu_clk_mux0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Datasheet names this field as "Mux1_divn_tcnt" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static struct clk_regmap sm1_dsu_clk_mux1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .offset = HHI_SYS_CPU_CLK_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .width = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .name = "dsu_clk_dyn1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) &sm1_dsu_clk_premux1.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Datasheet names this field as "postmux1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static struct clk_regmap sm1_dsu_clk_postmux1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .offset = HHI_SYS_CPU_CLK_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .name = "dsu_clk_dyn1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) &sm1_dsu_clk_premux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) &sm1_dsu_clk_mux1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Datasheet names this field as "Final_dyn_mux_sel" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static struct clk_regmap sm1_dsu_clk_dyn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .offset = HHI_SYS_CPU_CLK_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .name = "dsu_clk_dyn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) &sm1_dsu_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) &sm1_dsu_clk_postmux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Datasheet names this field as "Final_mux_sel" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static struct clk_regmap sm1_dsu_final_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .offset = HHI_SYS_CPU_CLK_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .name = "dsu_clk_final",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) &sm1_dsu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) &g12a_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static struct clk_regmap sm1_cpu1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .offset = HHI_SYS_CPU_CLK_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .name = "cpu1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) &g12a_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* This CPU also have a dedicated clock tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct clk_regmap sm1_cpu2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .offset = HHI_SYS_CPU_CLK_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .name = "cpu2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) &g12a_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* This CPU also have a dedicated clock tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static struct clk_regmap sm1_cpu3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .offset = HHI_SYS_CPU_CLK_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .shift = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .name = "cpu3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) &g12a_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* This CPU also have a dedicated clock tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static struct clk_regmap sm1_dsu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .offset = HHI_SYS_CPU_CLK_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .shift = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .name = "dsu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) &g12a_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &sm1_dsu_final_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Wait for clock propagation before/after changing the mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static struct notifier_block g12a_cpu_clk_mux_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .notifier_call = g12a_cpu_clk_mux_notifier_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct g12a_cpu_clk_postmux_nb_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct clk_hw *xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct clk_hw *cpu_clk_dyn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct clk_hw *cpu_clk_postmux0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct clk_hw *cpu_clk_postmux1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct clk_hw *cpu_clk_premux1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct g12a_cpu_clk_postmux_nb_data *nb_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * This notifier means cpu_clk_postmux0 clock will be changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * to feed cpu_clk, this is the current path :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * cpu_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * \- cpu_clk_dyn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * \- cpu_clk_postmux0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * \- cpu_clk_muxX_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * \- cpu_clk_premux0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * \- fclk_div3 or fclk_div2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * \- cpu_clk_premux0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * \- fclk_div3 or fclk_div2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* Setup cpu_clk_premux1 to xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) clk_hw_set_parent(nb_data->cpu_clk_premux1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) nb_data->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Setup cpu_clk_postmux1 to bypass divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) clk_hw_set_parent(nb_data->cpu_clk_postmux1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) nb_data->cpu_clk_premux1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Switch to parking clk on cpu_clk_postmux1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) clk_hw_set_parent(nb_data->cpu_clk_dyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) nb_data->cpu_clk_postmux1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * Now, cpu_clk is 24MHz in the current path :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * cpu_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * \- cpu_clk_dyn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * \- cpu_clk_postmux1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * \- cpu_clk_premux1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * \- xtal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * The cpu_clk_postmux0 has ben updated, now switch back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * cpu_clk_dyn to cpu_clk_postmux0 and take the changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * in account.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) clk_hw_set_parent(nb_data->cpu_clk_dyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) nb_data->cpu_clk_postmux0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * new path :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * cpu_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * \- cpu_clk_dyn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * \- cpu_clk_postmux0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * \- cpu_clk_muxX_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * \- cpu_clk_premux0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * \- fclk_div3 or fclk_div2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * \- cpu_clk_premux0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * \- fclk_div3 or fclk_div2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct g12a_sys_pll_nb_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct clk_hw *sys_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct clk_hw *cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct clk_hw *cpu_clk_dyn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct g12a_sys_pll_nb_data *nb_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) container_of(nb, struct g12a_sys_pll_nb_data, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * This notifier means sys_pll clock will be changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * to feed cpu_clk, this the current path :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * cpu_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * \- sys_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * \- sys_pll_dco
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* Configure cpu_clk to use cpu_clk_dyn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) clk_hw_set_parent(nb_data->cpu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) nb_data->cpu_clk_dyn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * Now, cpu_clk uses the dyn path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * cpu_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * \- cpu_clk_dyn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * \- cpu_clk_dynX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * \- cpu_clk_dynX_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * \- cpu_clk_dynX_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * \- xtal/fclk_div2/fclk_div3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * \- xtal/fclk_div2/fclk_div3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * The sys_pll has ben updated, now switch back cpu_clk to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * sys_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* Configure cpu_clk to use sys_pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) clk_hw_set_parent(nb_data->cpu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) nb_data->sys_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* new path :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * cpu_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * \- sys_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * \- sys_pll_dco
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .sys_pll = &g12a_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .cpu_clk = &g12a_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .nb.notifier_call = g12a_sys_pll_notifier_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* G12B first CPU cluster uses sys1_pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .sys_pll = &g12b_sys1_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .cpu_clk = &g12b_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .nb.notifier_call = g12a_sys_pll_notifier_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* G12B second CPU cluster uses sys_pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .sys_pll = &g12a_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .cpu_clk = &g12b_cpub_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .nb.notifier_call = g12a_sys_pll_notifier_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static struct clk_regmap g12a_cpu_clk_div16_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .name = "cpu_clk_div16_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) &g12a_cpu_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * This clock is used to debug the cpu_clk range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static struct clk_regmap g12b_cpub_clk_div16_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .offset = HHI_SYS_CPUB_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .name = "cpub_clk_div16_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) &g12b_cpub_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * This clock is used to debug the cpu_clk range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static struct clk_fixed_factor g12a_cpu_clk_div16 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .div = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .name = "cpu_clk_div16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) &g12a_cpu_clk_div16_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static struct clk_fixed_factor g12b_cpub_clk_div16 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .div = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .name = "cpub_clk_div16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) &g12b_cpub_clk_div16_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static struct clk_regmap g12a_cpu_clk_apb_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .name = "cpu_clk_apb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static struct clk_regmap g12a_cpu_clk_apb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .name = "cpu_clk_apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) &g12a_cpu_clk_apb_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * This clock is set by the ROM monitor code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static struct clk_regmap g12a_cpu_clk_atb_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .name = "cpu_clk_atb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static struct clk_regmap g12a_cpu_clk_atb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .bit_idx = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .name = "cpu_clk_atb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) &g12a_cpu_clk_atb_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * This clock is set by the ROM monitor code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static struct clk_regmap g12a_cpu_clk_axi_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .name = "cpu_clk_axi_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static struct clk_regmap g12a_cpu_clk_axi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .bit_idx = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .name = "cpu_clk_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) &g12a_cpu_clk_axi_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * This clock is set by the ROM monitor code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static struct clk_regmap g12a_cpu_clk_trace_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .name = "cpu_clk_trace_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * G12A and G12B have different cpu_clks (with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * different struct clk_hw). We fallback to the global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * naming string mechanism so cpu_clk_trace_div picks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * up the appropriate one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .name = "cpu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static struct clk_regmap g12a_cpu_clk_trace = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .offset = HHI_SYS_CPU_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .bit_idx = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .name = "cpu_clk_trace",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &g12a_cpu_clk_trace_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * This clock is set by the ROM monitor code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static struct clk_fixed_factor g12b_cpub_clk_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .name = "cpub_clk_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) &g12b_cpub_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static struct clk_fixed_factor g12b_cpub_clk_div3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .div = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .name = "cpub_clk_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) &g12b_cpub_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static struct clk_fixed_factor g12b_cpub_clk_div4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .name = "cpub_clk_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) &g12b_cpub_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static struct clk_fixed_factor g12b_cpub_clk_div5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .div = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .name = "cpub_clk_div5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) &g12b_cpub_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static struct clk_fixed_factor g12b_cpub_clk_div6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .div = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .name = "cpub_clk_div6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) &g12b_cpub_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static struct clk_fixed_factor g12b_cpub_clk_div7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .div = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .name = "cpub_clk_div7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) &g12b_cpub_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static struct clk_fixed_factor g12b_cpub_clk_div8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .div = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .name = "cpub_clk_div8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) &g12b_cpub_clk.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static struct clk_regmap g12b_cpub_clk_apb_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .offset = HHI_SYS_CPUB_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .table = mux_table_cpub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .name = "cpub_clk_apb_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) &g12b_cpub_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) &g12b_cpub_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) &g12b_cpub_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) &g12b_cpub_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) &g12b_cpub_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) &g12b_cpub_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) &g12b_cpub_clk_div8.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static struct clk_regmap g12b_cpub_clk_apb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .offset = HHI_SYS_CPUB_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .bit_idx = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .flags = CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .name = "cpub_clk_apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) &g12b_cpub_clk_apb_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * This clock is set by the ROM monitor code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static struct clk_regmap g12b_cpub_clk_atb_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .offset = HHI_SYS_CPUB_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .table = mux_table_cpub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .name = "cpub_clk_atb_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) &g12b_cpub_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) &g12b_cpub_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) &g12b_cpub_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) &g12b_cpub_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) &g12b_cpub_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) &g12b_cpub_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) &g12b_cpub_clk_div8.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static struct clk_regmap g12b_cpub_clk_atb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .offset = HHI_SYS_CPUB_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .bit_idx = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .flags = CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .name = "cpub_clk_atb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) &g12b_cpub_clk_atb_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * This clock is set by the ROM monitor code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static struct clk_regmap g12b_cpub_clk_axi_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .offset = HHI_SYS_CPUB_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .table = mux_table_cpub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .name = "cpub_clk_axi_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) &g12b_cpub_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) &g12b_cpub_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) &g12b_cpub_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) &g12b_cpub_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) &g12b_cpub_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) &g12b_cpub_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) &g12b_cpub_clk_div8.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static struct clk_regmap g12b_cpub_clk_axi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .offset = HHI_SYS_CPUB_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .bit_idx = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .flags = CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .name = "cpub_clk_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) &g12b_cpub_clk_axi_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * This clock is set by the ROM monitor code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static struct clk_regmap g12b_cpub_clk_trace_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .offset = HHI_SYS_CPUB_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .table = mux_table_cpub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .name = "cpub_clk_trace_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) &g12b_cpub_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) &g12b_cpub_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) &g12b_cpub_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) &g12b_cpub_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) &g12b_cpub_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) &g12b_cpub_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) &g12b_cpub_clk_div8.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static struct clk_regmap g12b_cpub_clk_trace = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .offset = HHI_SYS_CPUB_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .bit_idx = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .flags = CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .name = "cpub_clk_trace",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) &g12b_cpub_clk_trace_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) * This clock is set by the ROM monitor code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) * Linux should not change it at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) static const struct pll_mult_range g12a_gp0_pll_mult_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .min = 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .max = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) * Internal gp0 pll emulation configuration parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static const struct reg_sequence g12a_gp0_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static struct clk_regmap g12a_gp0_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .reg_off = HHI_GP0_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .reg_off = HHI_GP0_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .reg_off = HHI_GP0_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .reg_off = HHI_GP0_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .width = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .reg_off = HHI_GP0_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .reg_off = HHI_GP0_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .range = &g12a_gp0_pll_mult_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .init_regs = g12a_gp0_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .init_count = ARRAY_SIZE(g12a_gp0_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .name = "gp0_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static struct clk_regmap g12a_gp0_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .offset = HHI_GP0_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .flags = (CLK_DIVIDER_POWER_OF_TWO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .name = "gp0_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) &g12a_gp0_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) static struct clk_regmap sm1_gp1_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .reg_off = HHI_GP1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .reg_off = HHI_GP1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .reg_off = HHI_GP1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .reg_off = HHI_GP1_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .width = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .reg_off = HHI_GP1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .reg_off = HHI_GP1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .name = "gp1_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) /* This clock feeds the DSU, avoid disabling it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static struct clk_regmap sm1_gp1_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .offset = HHI_GP1_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .flags = (CLK_DIVIDER_POWER_OF_TWO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .name = "gp1_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) &sm1_gp1_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * Internal hifi pll emulation configuration parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static const struct reg_sequence g12a_hifi_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static struct clk_regmap g12a_hifi_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .reg_off = HHI_HIFI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .reg_off = HHI_HIFI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .reg_off = HHI_HIFI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .reg_off = HHI_HIFI_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .width = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .reg_off = HHI_HIFI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .reg_off = HHI_HIFI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .range = &g12a_gp0_pll_mult_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .init_regs = g12a_hifi_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .init_count = ARRAY_SIZE(g12a_hifi_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .flags = CLK_MESON_PLL_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .name = "hifi_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static struct clk_regmap g12a_hifi_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .offset = HHI_HIFI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .flags = (CLK_DIVIDER_POWER_OF_TWO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .name = "hifi_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) &g12a_hifi_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * 100MHz reference clock for the PCIe Analog PHY, and thus requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) * a strict register sequence to enable the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /* Keep a single entry table for recalc/round_rate() ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static const struct pll_params_table g12a_pcie_pll_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) PLL_PARAMS(150, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static struct clk_regmap g12a_pcie_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .reg_off = HHI_PCIE_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .reg_off = HHI_PCIE_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .reg_off = HHI_PCIE_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .reg_off = HHI_PCIE_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .reg_off = HHI_PCIE_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .reg_off = HHI_PCIE_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .table = g12a_pcie_pll_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .init_regs = g12a_pcie_pll_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .name = "pcie_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .ops = &meson_clk_pcie_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .name = "pcie_pll_dco_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) &g12a_pcie_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static struct clk_regmap g12a_pcie_pll_od = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .offset = HHI_PCIE_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .flags = CLK_DIVIDER_ROUND_CLOSEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) CLK_DIVIDER_ALLOW_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .name = "pcie_pll_od",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) &g12a_pcie_pll_dco_div2.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static struct clk_fixed_factor g12a_pcie_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .name = "pcie_pll_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) &g12a_pcie_pll_od.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static struct clk_regmap g12a_hdmi_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .reg_off = HHI_HDMI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .reg_off = HHI_HDMI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .reg_off = HHI_HDMI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .reg_off = HHI_HDMI_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .reg_off = HHI_HDMI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .reg_off = HHI_HDMI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .name = "hdmi_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) * Display directly handle hdmi pll registers ATM, we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) * NOCACHE to keep our view of the clock as accurate as possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) static struct clk_regmap g12a_hdmi_pll_od = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .offset = HHI_HDMI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .name = "hdmi_pll_od",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) &g12a_hdmi_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static struct clk_regmap g12a_hdmi_pll_od2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .offset = HHI_HDMI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .name = "hdmi_pll_od2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) &g12a_hdmi_pll_od.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static struct clk_regmap g12a_hdmi_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .offset = HHI_HDMI_PLL_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .name = "hdmi_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) &g12a_hdmi_pll_od2.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static struct clk_fixed_factor g12a_fclk_div4_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .name = "fclk_div4_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) static struct clk_regmap g12a_fclk_div4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .offset = HHI_FIX_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .bit_idx = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .name = "fclk_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) &g12a_fclk_div4_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static struct clk_fixed_factor g12a_fclk_div5_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .div = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .name = "fclk_div5_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) static struct clk_regmap g12a_fclk_div5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .offset = HHI_FIX_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .bit_idx = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .name = "fclk_div5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) &g12a_fclk_div5_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) static struct clk_fixed_factor g12a_fclk_div7_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .div = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .name = "fclk_div7_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) static struct clk_regmap g12a_fclk_div7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .offset = HHI_FIX_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .bit_idx = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .name = "fclk_div7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) &g12a_fclk_div7_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) static struct clk_fixed_factor g12a_fclk_div2p5_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .div = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .name = "fclk_div2p5_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) &g12a_fixed_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) static struct clk_regmap g12a_fclk_div2p5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .offset = HHI_FIX_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .bit_idx = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .name = "fclk_div2p5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) &g12a_fclk_div2p5_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) static struct clk_fixed_factor g12a_mpll_50m_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .div = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .name = "mpll_50m_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) &g12a_fixed_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) static struct clk_regmap g12a_mpll_50m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .offset = HHI_FIX_PLL_CNTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .name = "mpll_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) { .hw = &g12a_mpll_50m_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) static struct clk_fixed_factor g12a_mpll_prediv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .name = "mpll_prediv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) &g12a_fixed_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) static const struct reg_sequence g12a_mpll0_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) static struct clk_regmap g12a_mpll0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .reg_off = HHI_MPLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .reg_off = HHI_MPLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .reg_off = HHI_MPLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .ssen = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .reg_off = HHI_MPLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .init_regs = g12a_mpll0_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .name = "mpll0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) &g12a_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static struct clk_regmap g12a_mpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .offset = HHI_MPLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .bit_idx = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .name = "mpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) static const struct reg_sequence g12a_mpll1_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) { .reg = HHI_MPLL_CNTL4, .def = 0x40000033 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static struct clk_regmap g12a_mpll1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .reg_off = HHI_MPLL_CNTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .reg_off = HHI_MPLL_CNTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .reg_off = HHI_MPLL_CNTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .ssen = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .reg_off = HHI_MPLL_CNTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .init_regs = g12a_mpll1_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .name = "mpll1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) &g12a_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) static struct clk_regmap g12a_mpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .offset = HHI_MPLL_CNTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .bit_idx = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .name = "mpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) static const struct reg_sequence g12a_mpll2_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) static struct clk_regmap g12a_mpll2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .reg_off = HHI_MPLL_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .reg_off = HHI_MPLL_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .reg_off = HHI_MPLL_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .ssen = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .reg_off = HHI_MPLL_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .init_regs = g12a_mpll2_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .name = "mpll2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) &g12a_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static struct clk_regmap g12a_mpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .offset = HHI_MPLL_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .bit_idx = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .name = "mpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) static const struct reg_sequence g12a_mpll3_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) static struct clk_regmap g12a_mpll3_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .ssen = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .init_regs = g12a_mpll3_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .name = "mpll3_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) &g12a_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) static struct clk_regmap g12a_mpll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .offset = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .bit_idx = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .name = "mpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) static const struct clk_parent_data clk81_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) { .hw = &g12a_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) { .hw = &g12a_mpll1.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) { .hw = &g12a_mpll2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) { .hw = &g12a_fclk_div4.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) { .hw = &g12a_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static struct clk_regmap g12a_mpeg_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .table = mux_table_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .name = "mpeg_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .parent_data = clk81_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .num_parents = ARRAY_SIZE(clk81_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static struct clk_regmap g12a_mpeg_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .name = "mpeg_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) &g12a_mpeg_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) static struct clk_regmap g12a_clk81 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .name = "clk81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) &g12a_mpeg_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) { .hw = &g12a_fclk_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) { .hw = &g12a_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) { .hw = &g12a_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) * Following these parent clocks, we should also have had mpll2, mpll3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) * and gp0_pll but these clocks are too precious to be used here. All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) * the necessary rates for MMC and NAND operation can be acheived using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) * g12a_ee_core or fclk_div clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) /* SDIO clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .name = "sd_emmc_a_clk0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .parent_data = g12a_sd_emmc_clk0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .name = "sd_emmc_a_clk0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) &g12a_sd_emmc_a_clk0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) static struct clk_regmap g12a_sd_emmc_a_clk0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .name = "sd_emmc_a_clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) &g12a_sd_emmc_a_clk0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) /* SDcard clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .name = "sd_emmc_b_clk0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .parent_data = g12a_sd_emmc_clk0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .name = "sd_emmc_b_clk0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) &g12a_sd_emmc_b_clk0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) static struct clk_regmap g12a_sd_emmc_b_clk0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .bit_idx = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .name = "sd_emmc_b_clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) &g12a_sd_emmc_b_clk0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) /* EMMC/NAND clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .name = "sd_emmc_c_clk0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .parent_data = g12a_sd_emmc_clk0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .name = "sd_emmc_c_clk0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) &g12a_sd_emmc_c_clk0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) static struct clk_regmap g12a_sd_emmc_c_clk0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .name = "sd_emmc_c_clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) &g12a_sd_emmc_c_clk0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) /* Video Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static struct clk_regmap g12a_vid_pll_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .data = &(struct meson_vid_pll_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .val = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .reg_off = HHI_VID_PLL_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .width = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .reg_off = HHI_VID_PLL_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .name = "vid_pll_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .ops = &meson_vid_pll_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) &g12a_vid_pll_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) &g12a_hdmi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) static struct clk_regmap g12a_vid_pll_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .offset = HHI_VID_PLL_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .name = "vid_pll_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) * bit 18 selects from 2 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) * vid_pll_div or hdmi_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .parent_hws = g12a_vid_pll_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) static struct clk_regmap g12a_vid_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .offset = HHI_VID_PLL_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .bit_idx = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .name = "vid_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) &g12a_vid_pll_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) /* VPU Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) static const struct clk_hw *g12a_vpu_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) &g12a_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) &g12a_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) &g12a_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) &g12a_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) &g12a_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) &g12a_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) &g12a_hifi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) &g12a_gp0_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) static struct clk_regmap g12a_vpu_0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .name = "vpu_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .parent_hws = g12a_vpu_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) static struct clk_regmap g12a_vpu_0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .name = "vpu_0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) static struct clk_regmap g12a_vpu_0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .name = "vpu_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) static struct clk_regmap g12a_vpu_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .name = "vpu_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .parent_hws = g12a_vpu_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) static struct clk_regmap g12a_vpu_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) .name = "vpu_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) static struct clk_regmap g12a_vpu_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .name = "vpu_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) static struct clk_regmap g12a_vpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .offset = HHI_VPU_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .name = "vpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) * bit 31 selects from 2 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) * vpu_0 or vpu_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) &g12a_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) &g12a_vpu_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) /* VDEC clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) static const struct clk_hw *g12a_vdec_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) &g12a_fclk_div2p5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) &g12a_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) &g12a_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) &g12a_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) &g12a_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) &g12a_hifi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) &g12a_gp0_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) static struct clk_regmap g12a_vdec_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .name = "vdec_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .parent_hws = g12a_vdec_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) static struct clk_regmap g12a_vdec_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .name = "vdec_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) &g12a_vdec_1_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) static struct clk_regmap g12a_vdec_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .offset = HHI_VDEC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .name = "vdec_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) &g12a_vdec_1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) static struct clk_regmap g12a_vdec_hevcf_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .name = "vdec_hevcf_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) .parent_hws = g12a_vdec_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) static struct clk_regmap g12a_vdec_hevcf_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .name = "vdec_hevcf_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) &g12a_vdec_hevcf_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) static struct clk_regmap g12a_vdec_hevcf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) .name = "vdec_hevcf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) &g12a_vdec_hevcf_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) static struct clk_regmap g12a_vdec_hevc_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) .name = "vdec_hevc_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) .parent_hws = g12a_vdec_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) static struct clk_regmap g12a_vdec_hevc_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) .name = "vdec_hevc_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) &g12a_vdec_hevc_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) static struct clk_regmap g12a_vdec_hevc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .offset = HHI_VDEC2_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) .name = "vdec_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) &g12a_vdec_hevc_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) /* VAPB Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) static const struct clk_hw *g12a_vapb_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) &g12a_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) &g12a_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) &g12a_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) &g12a_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) &g12a_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) &g12a_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) &g12a_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) &g12a_fclk_div2p5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) static struct clk_regmap g12a_vapb_0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) .name = "vapb_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .parent_hws = g12a_vapb_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) static struct clk_regmap g12a_vapb_0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .name = "vapb_0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) &g12a_vapb_0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) static struct clk_regmap g12a_vapb_0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .name = "vapb_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) &g12a_vapb_0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) static struct clk_regmap g12a_vapb_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .name = "vapb_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .parent_hws = g12a_vapb_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) static struct clk_regmap g12a_vapb_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) .name = "vapb_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) &g12a_vapb_1_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) static struct clk_regmap g12a_vapb_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) .name = "vapb_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) &g12a_vapb_1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) static struct clk_regmap g12a_vapb_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) .mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) .name = "vapb_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) * bit 31 selects from 2 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) * vapb_0 or vapb_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) &g12a_vapb_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) &g12a_vapb_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) static struct clk_regmap g12a_vapb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) .offset = HHI_VAPBCLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) .bit_idx = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) .name = "vapb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) static const struct clk_hw *g12a_vclk_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) &g12a_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) &g12a_gp0_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) &g12a_hifi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) &g12a_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) &g12a_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) &g12a_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) &g12a_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) &g12a_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) static struct clk_regmap g12a_vclk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) .name = "vclk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) .parent_hws = g12a_vclk_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) static struct clk_regmap g12a_vclk2_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) .name = "vclk2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) .parent_hws = g12a_vclk_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) static struct clk_regmap g12a_vclk_input = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) .bit_idx = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) .name = "vclk_input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) static struct clk_regmap g12a_vclk2_input = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) .bit_idx = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) .name = "vclk2_input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) static struct clk_regmap g12a_vclk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) .name = "vclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) &g12a_vclk_input.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) static struct clk_regmap g12a_vclk2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) .name = "vclk2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) &g12a_vclk2_input.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) static struct clk_regmap g12a_vclk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) .bit_idx = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) .name = "vclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) static struct clk_regmap g12a_vclk2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) .bit_idx = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) .name = "vclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) static struct clk_regmap g12a_vclk_div1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) .name = "vclk_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) static struct clk_regmap g12a_vclk_div2_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) .name = "vclk_div2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) static struct clk_regmap g12a_vclk_div4_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) .bit_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) .name = "vclk_div4_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) static struct clk_regmap g12a_vclk_div6_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) .bit_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) .name = "vclk_div6_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) static struct clk_regmap g12a_vclk_div12_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) .offset = HHI_VID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) .bit_idx = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) .name = "vclk_div12_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) static struct clk_regmap g12a_vclk2_div1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) .name = "vclk2_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) static struct clk_regmap g12a_vclk2_div2_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) .bit_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) .name = "vclk2_div2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) static struct clk_regmap g12a_vclk2_div4_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) .bit_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) .name = "vclk2_div4_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) static struct clk_regmap g12a_vclk2_div6_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) .bit_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) .name = "vclk2_div6_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) static struct clk_regmap g12a_vclk2_div12_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) .offset = HHI_VIID_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) .bit_idx = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) .name = "vclk2_div12_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) static struct clk_fixed_factor g12a_vclk_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) .name = "vclk_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) &g12a_vclk_div2_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) static struct clk_fixed_factor g12a_vclk_div4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) .name = "vclk_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) &g12a_vclk_div4_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) static struct clk_fixed_factor g12a_vclk_div6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) .div = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) .name = "vclk_div6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) &g12a_vclk_div6_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) static struct clk_fixed_factor g12a_vclk_div12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) .div = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) .name = "vclk_div12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) &g12a_vclk_div12_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) static struct clk_fixed_factor g12a_vclk2_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) .name = "vclk2_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) &g12a_vclk2_div2_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) static struct clk_fixed_factor g12a_vclk2_div4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) .name = "vclk2_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) &g12a_vclk2_div4_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) static struct clk_fixed_factor g12a_vclk2_div6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) .div = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) .name = "vclk2_div6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) &g12a_vclk2_div6_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) static struct clk_fixed_factor g12a_vclk2_div12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) .div = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) .name = "vclk2_div12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) &g12a_vclk2_div12_en.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) static const struct clk_hw *g12a_cts_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) &g12a_vclk_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) &g12a_vclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) &g12a_vclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) &g12a_vclk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) &g12a_vclk_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) &g12a_vclk2_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) &g12a_vclk2_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) &g12a_vclk2_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) &g12a_vclk2_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) &g12a_vclk2_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) static struct clk_regmap g12a_cts_enci_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) .table = mux_table_cts_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) .name = "cts_enci_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) .parent_hws = g12a_cts_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) static struct clk_regmap g12a_cts_encp_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) .offset = HHI_VID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) .table = mux_table_cts_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) .name = "cts_encp_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) .parent_hws = g12a_cts_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) static struct clk_regmap g12a_cts_vdac_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) .offset = HHI_VIID_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) .table = mux_table_cts_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) .name = "cts_vdac_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) .parent_hws = g12a_cts_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) /* TOFIX: add support for cts_tcon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) &g12a_vclk_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) &g12a_vclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) &g12a_vclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) &g12a_vclk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) &g12a_vclk_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) &g12a_vclk2_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) &g12a_vclk2_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) &g12a_vclk2_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) &g12a_vclk2_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) &g12a_vclk2_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) static struct clk_regmap g12a_hdmi_tx_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) .table = mux_table_hdmi_tx_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) .name = "hdmi_tx_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) .parent_hws = g12a_cts_hdmi_tx_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) static struct clk_regmap g12a_cts_enci = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) .name = "cts_enci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) &g12a_cts_enci_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) static struct clk_regmap g12a_cts_encp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) .bit_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) .name = "cts_encp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) &g12a_cts_encp_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) static struct clk_regmap g12a_cts_vdac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) .bit_idx = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) .name = "cts_vdac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) &g12a_cts_vdac_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) static struct clk_regmap g12a_hdmi_tx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) .offset = HHI_VID_CLK_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) .bit_idx = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) .name = "hdmi_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) &g12a_hdmi_tx_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) /* HDMI Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) static const struct clk_parent_data g12a_hdmi_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) { .hw = &g12a_fclk_div4.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) { .hw = &g12a_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) static struct clk_regmap g12a_hdmi_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) .flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) .name = "hdmi_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) .parent_data = g12a_hdmi_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) .num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) static struct clk_regmap g12a_hdmi_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) .name = "hdmi_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) static struct clk_regmap g12a_hdmi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) .offset = HHI_HDMI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) .name = "hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) * muxed by a glitch-free switch. The CCF can manage this glitch-free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) * mux because it does top-to-bottom updates the each clock tree and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) { .hw = &g12a_gp0_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) { .hw = &g12a_hifi_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) { .hw = &g12a_fclk_div2p5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) { .hw = &g12a_fclk_div4.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) { .hw = &g12a_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) { .hw = &g12a_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) static struct clk_regmap g12a_mali_0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) .name = "mali_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) .parent_data = g12a_mali_0_1_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) * Don't request the parent to change the rate because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) * all GPU frequencies can be derived from the fclk_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) * clocks and one special GP0_PLL setting. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) * important because we need the MPLL clocks for audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) static struct clk_regmap g12a_mali_0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) .name = "mali_0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) &g12a_mali_0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) static struct clk_regmap g12a_mali_0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) .name = "mali_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) &g12a_mali_0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) static struct clk_regmap g12a_mali_1_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) .name = "mali_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) .parent_data = g12a_mali_0_1_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) * Don't request the parent to change the rate because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) * all GPU frequencies can be derived from the fclk_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) * clocks and one special GP0_PLL setting. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) * important because we need the MPLL clocks for audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) static struct clk_regmap g12a_mali_1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) .name = "mali_1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) &g12a_mali_1_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) static struct clk_regmap g12a_mali_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) .name = "mali_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) &g12a_mali_1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) static const struct clk_hw *g12a_mali_parent_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) &g12a_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) &g12a_mali_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) static struct clk_regmap g12a_mali = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) .offset = HHI_MALI_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) .mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) .name = "mali",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) .parent_hws = g12a_mali_parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) static struct clk_regmap g12a_ts_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) .offset = HHI_TS_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) .name = "ts_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) static struct clk_regmap g12a_ts = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) .offset = HHI_TS_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) .name = "ts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) &g12a_ts_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) /* SPICC SCLK source clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) static const struct clk_parent_data spicc_sclk_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) { .hw = &g12a_clk81.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) { .hw = &g12a_fclk_div4.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) { .hw = &g12a_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) { .hw = &g12a_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) { .hw = &g12a_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) static struct clk_regmap g12a_spicc0_sclk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) .offset = HHI_SPICC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) .mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) .shift = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) .name = "spicc0_sclk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) .parent_data = spicc_sclk_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) .num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) static struct clk_regmap g12a_spicc0_sclk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) .offset = HHI_SPICC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) .width = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) .name = "spicc0_sclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) &g12a_spicc0_sclk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) static struct clk_regmap g12a_spicc0_sclk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) .offset = HHI_SPICC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) .bit_idx = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) .name = "spicc0_sclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) &g12a_spicc0_sclk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) static struct clk_regmap g12a_spicc1_sclk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) .offset = HHI_SPICC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) .mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) .shift = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) .name = "spicc1_sclk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) .parent_data = spicc_sclk_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) .num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) static struct clk_regmap g12a_spicc1_sclk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) .offset = HHI_SPICC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) .width = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) .name = "spicc1_sclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) &g12a_spicc1_sclk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) static struct clk_regmap g12a_spicc1_sclk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) .offset = HHI_SPICC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) .bit_idx = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) .name = "spicc1_sclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) &g12a_spicc1_sclk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) /* Neural Network Accelerator source clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) static const struct clk_parent_data nna_clk_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) { .hw = &g12a_gp0_pll.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) { .hw = &g12a_hifi_pll.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) { .hw = &g12a_fclk_div2p5.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) { .hw = &g12a_fclk_div3.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) { .hw = &g12a_fclk_div4.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) { .hw = &g12a_fclk_div5.hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) { .hw = &g12a_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) static struct clk_regmap sm1_nna_axi_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) .offset = HHI_NNA_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) .mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) .name = "nna_axi_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) .parent_data = nna_clk_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) .num_parents = ARRAY_SIZE(nna_clk_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) static struct clk_regmap sm1_nna_axi_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) .offset = HHI_NNA_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) .name = "nna_axi_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) &sm1_nna_axi_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) static struct clk_regmap sm1_nna_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) .offset = HHI_NNA_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) .name = "nna_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) &sm1_nna_axi_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) static struct clk_regmap sm1_nna_core_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) .offset = HHI_NNA_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) .mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) .name = "nna_core_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) .parent_data = nna_clk_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) .num_parents = ARRAY_SIZE(nna_clk_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) static struct clk_regmap sm1_nna_core_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) .offset = HHI_NNA_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) .name = "nna_core_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) &sm1_nna_core_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) static struct clk_regmap sm1_nna_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) .offset = HHI_NNA_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) .name = "nna_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) &sm1_nna_core_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) #define MESON_GATE(_name, _reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) #define MESON_GATE_RO(_name, _reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) /* Everything Else (EE) domain gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) /* Array of all clocks provided by this provider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) static struct clk_hw_onecell_data g12a_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) [CLKID_CLK81] = &g12a_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) [CLKID_MPLL0] = &g12a_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) [CLKID_MPLL1] = &g12a_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) [CLKID_MPLL2] = &g12a_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) [CLKID_MPLL3] = &g12a_mpll3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) [CLKID_DDR] = &g12a_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) [CLKID_DOS] = &g12a_dos.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) [CLKID_ISA] = &g12a_isa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) [CLKID_PL301] = &g12a_pl301.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) [CLKID_PERIPHS] = &g12a_periphs.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) [CLKID_SPICC0] = &g12a_spicc_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) [CLKID_I2C] = &g12a_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) [CLKID_SANA] = &g12a_sana.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) [CLKID_SD] = &g12a_sd.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) [CLKID_RNG0] = &g12a_rng0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) [CLKID_UART0] = &g12a_uart0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) [CLKID_SPICC1] = &g12a_spicc_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) [CLKID_AUDIO] = &g12a_audio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) [CLKID_ETH] = &g12a_eth_core.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) [CLKID_DEMUX] = &g12a_demux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) [CLKID_ADC] = &g12a_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) [CLKID_UART1] = &g12a_uart1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) [CLKID_G2D] = &g12a_g2d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) [CLKID_RESET] = &g12a_reset.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) [CLKID_PARSER] = &g12a_parser.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) [CLKID_USB] = &g12a_usb_general.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) [CLKID_BT656] = &g12a_bt656.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) [CLKID_UART2] = &g12a_uart2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) [CLKID_GIC] = &g12a_gic.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) [CLKID_IEC958] = &g12a_iec958_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) [CLKID_ENC480P] = &g12a_enc480p.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) [CLKID_RNG1] = &g12a_rng1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) [CLKID_DMA] = &g12a_dma.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) [CLKID_EFUSE] = &g12a_efuse.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) [CLKID_VPU_0] = &g12a_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) [CLKID_VPU_1] = &g12a_vpu_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) [CLKID_VPU] = &g12a_vpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) [CLKID_VAPB_0] = &g12a_vapb_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) [CLKID_VAPB_1] = &g12a_vapb_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) [CLKID_VAPB] = &g12a_vapb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) [CLKID_VCLK] = &g12a_vclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) [CLKID_VCLK2] = &g12a_vclk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) [CLKID_HDMI] = &g12a_hdmi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) [CLKID_MALI_0] = &g12a_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) [CLKID_MALI_1] = &g12a_mali_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) [CLKID_MALI] = &g12a_mali.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) [CLKID_VDEC_1] = &g12a_vdec_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) [CLKID_TS_DIV] = &g12a_ts_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) [CLKID_TS] = &g12a_ts.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) [NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) .num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) static struct clk_hw_onecell_data g12b_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) [CLKID_CLK81] = &g12a_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) [CLKID_MPLL0] = &g12a_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) [CLKID_MPLL1] = &g12a_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) [CLKID_MPLL2] = &g12a_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) [CLKID_MPLL3] = &g12a_mpll3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) [CLKID_DDR] = &g12a_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) [CLKID_DOS] = &g12a_dos.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) [CLKID_ISA] = &g12a_isa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) [CLKID_PL301] = &g12a_pl301.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) [CLKID_PERIPHS] = &g12a_periphs.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) [CLKID_SPICC0] = &g12a_spicc_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) [CLKID_I2C] = &g12a_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) [CLKID_SANA] = &g12a_sana.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) [CLKID_SD] = &g12a_sd.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) [CLKID_RNG0] = &g12a_rng0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) [CLKID_UART0] = &g12a_uart0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) [CLKID_SPICC1] = &g12a_spicc_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) [CLKID_AUDIO] = &g12a_audio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) [CLKID_ETH] = &g12a_eth_core.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) [CLKID_DEMUX] = &g12a_demux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) [CLKID_ADC] = &g12a_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) [CLKID_UART1] = &g12a_uart1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) [CLKID_G2D] = &g12a_g2d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) [CLKID_RESET] = &g12a_reset.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) [CLKID_PARSER] = &g12a_parser.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) [CLKID_USB] = &g12a_usb_general.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) [CLKID_BT656] = &g12a_bt656.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) [CLKID_UART2] = &g12a_uart2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) [CLKID_GIC] = &g12a_gic.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) [CLKID_IEC958] = &g12a_iec958_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) [CLKID_ENC480P] = &g12a_enc480p.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) [CLKID_RNG1] = &g12a_rng1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) [CLKID_DMA] = &g12a_dma.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) [CLKID_EFUSE] = &g12a_efuse.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) [CLKID_VPU_0] = &g12a_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) [CLKID_VPU_1] = &g12a_vpu_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) [CLKID_VPU] = &g12a_vpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) [CLKID_VAPB_0] = &g12a_vapb_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) [CLKID_VAPB_1] = &g12a_vapb_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) [CLKID_VAPB] = &g12a_vapb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) [CLKID_VCLK] = &g12a_vclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) [CLKID_VCLK2] = &g12a_vclk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) [CLKID_HDMI] = &g12a_hdmi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) [CLKID_MALI_0] = &g12a_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) [CLKID_MALI_1] = &g12a_mali_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) [CLKID_MALI] = &g12a_mali.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) [CLKID_VDEC_1] = &g12a_vdec_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) [CLKID_TS_DIV] = &g12a_ts_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) [CLKID_TS] = &g12a_ts.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) [NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) .num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) static struct clk_hw_onecell_data sm1_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) [CLKID_CLK81] = &g12a_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) [CLKID_MPLL0] = &g12a_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) [CLKID_MPLL1] = &g12a_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) [CLKID_MPLL2] = &g12a_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) [CLKID_MPLL3] = &g12a_mpll3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) [CLKID_DDR] = &g12a_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) [CLKID_DOS] = &g12a_dos.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) [CLKID_ISA] = &g12a_isa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) [CLKID_PL301] = &g12a_pl301.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) [CLKID_PERIPHS] = &g12a_periphs.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) [CLKID_SPICC0] = &g12a_spicc_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) [CLKID_I2C] = &g12a_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) [CLKID_SANA] = &g12a_sana.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) [CLKID_SD] = &g12a_sd.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) [CLKID_RNG0] = &g12a_rng0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) [CLKID_UART0] = &g12a_uart0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) [CLKID_SPICC1] = &g12a_spicc_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) [CLKID_AUDIO] = &g12a_audio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) [CLKID_ETH] = &g12a_eth_core.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) [CLKID_DEMUX] = &g12a_demux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) [CLKID_ADC] = &g12a_adc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) [CLKID_UART1] = &g12a_uart1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) [CLKID_G2D] = &g12a_g2d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) [CLKID_RESET] = &g12a_reset.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) [CLKID_PARSER] = &g12a_parser.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) [CLKID_USB] = &g12a_usb_general.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) [CLKID_BT656] = &g12a_bt656.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) [CLKID_UART2] = &g12a_uart2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) [CLKID_GIC] = &g12a_gic.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) [CLKID_IEC958] = &g12a_iec958_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) [CLKID_ENC480P] = &g12a_enc480p.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) [CLKID_RNG1] = &g12a_rng1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) [CLKID_DMA] = &g12a_dma.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) [CLKID_EFUSE] = &g12a_efuse.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) [CLKID_VPU_0] = &g12a_vpu_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) [CLKID_VPU_1] = &g12a_vpu_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) [CLKID_VPU] = &g12a_vpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) [CLKID_VAPB_0] = &g12a_vapb_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) [CLKID_VAPB_1] = &g12a_vapb_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) [CLKID_VAPB] = &g12a_vapb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) [CLKID_VCLK] = &g12a_vclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) [CLKID_VCLK2] = &g12a_vclk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) [CLKID_HDMI] = &g12a_hdmi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) [CLKID_MALI_0] = &g12a_mali_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) [CLKID_MALI_1] = &g12a_mali_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) [CLKID_MALI] = &g12a_mali.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) [CLKID_VDEC_1] = &g12a_vdec_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) [CLKID_TS_DIV] = &g12a_ts_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) [CLKID_TS] = &g12a_ts.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) [NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) .num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) /* Convenience table to populate regmap in .probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) static struct clk_regmap *const g12a_clk_regmaps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) &g12a_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) &g12a_dos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) &g12a_ddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) &g12a_audio_locker,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) &g12a_mipi_dsi_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) &g12a_eth_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) &g12a_isa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) &g12a_pl301,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) &g12a_periphs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) &g12a_spicc_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) &g12a_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) &g12a_sana,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) &g12a_sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) &g12a_rng0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) &g12a_uart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) &g12a_spicc_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) &g12a_hiu_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) &g12a_mipi_dsi_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) &g12a_assist_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) &g12a_emmc_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) &g12a_emmc_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) &g12a_emmc_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) &g12a_audio_codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) &g12a_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) &g12a_eth_core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) &g12a_demux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) &g12a_audio_ififo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) &g12a_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) &g12a_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) &g12a_g2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) &g12a_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) &g12a_pcie_comb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) &g12a_parser,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) &g12a_usb_general,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) &g12a_pcie_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) &g12a_ahb_arb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) &g12a_ahb_data_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) &g12a_ahb_ctrl_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) &g12a_htx_hdcp22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) &g12a_htx_pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) &g12a_bt656,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) &g12a_usb1_to_ddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) &g12a_mmc_pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) &g12a_uart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) &g12a_vpu_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) &g12a_gic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) &g12a_sd_emmc_a_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) &g12a_sd_emmc_b_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) &g12a_sd_emmc_c_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) &g12a_mpeg_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) &g12a_sd_emmc_a_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) &g12a_sd_emmc_b_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) &g12a_sd_emmc_c_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) &g12a_mpeg_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) &g12a_sd_emmc_a_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) &g12a_sd_emmc_b_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) &g12a_sd_emmc_c_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) &g12a_mpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) &g12a_mpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) &g12a_mpll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) &g12a_mpll3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) &g12a_mpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) &g12a_mpll1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) &g12a_mpll2_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) &g12a_mpll3_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) &g12a_fixed_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) &g12a_sys_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) &g12a_gp0_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) &g12a_hifi_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) &g12a_vclk2_venci0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) &g12a_vclk2_venci1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) &g12a_vclk2_vencp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) &g12a_vclk2_vencp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) &g12a_vclk2_venct0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) &g12a_vclk2_venct1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) &g12a_vclk2_other,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) &g12a_vclk2_enci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) &g12a_vclk2_encp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) &g12a_dac_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) &g12a_aoclk_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) &g12a_iec958_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) &g12a_enc480p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) &g12a_rng1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) &g12a_vclk2_enct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) &g12a_vclk2_encl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) &g12a_vclk2_venclmmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) &g12a_vclk2_vencl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) &g12a_vclk2_other1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) &g12a_fixed_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) &g12a_sys_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) &g12a_gp0_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) &g12a_hifi_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) &g12a_fclk_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) &g12a_fclk_div3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) &g12a_fclk_div4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) &g12a_fclk_div5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) &g12a_fclk_div7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) &g12a_fclk_div2p5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) &g12a_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) &g12a_efuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) &g12a_rom_boot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) &g12a_reset_sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) &g12a_sec_ahb_apb3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) &g12a_vpu_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) &g12a_vpu_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) &g12a_vpu_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) &g12a_vpu_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) &g12a_vpu_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) &g12a_vpu_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) &g12a_vpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) &g12a_vapb_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) &g12a_vapb_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) &g12a_vapb_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) &g12a_vapb_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) &g12a_vapb_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) &g12a_vapb_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) &g12a_vapb_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) &g12a_vapb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) &g12a_hdmi_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) &g12a_hdmi_pll_od,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) &g12a_hdmi_pll_od2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) &g12a_hdmi_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) &g12a_vid_pll_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) &g12a_vid_pll_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) &g12a_vid_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) &g12a_vclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) &g12a_vclk2_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) &g12a_vclk_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) &g12a_vclk2_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) &g12a_vclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) &g12a_vclk2_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) &g12a_vclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) &g12a_vclk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) &g12a_vclk_div1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) &g12a_vclk_div2_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) &g12a_vclk_div4_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) &g12a_vclk_div6_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) &g12a_vclk_div12_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) &g12a_vclk2_div1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) &g12a_vclk2_div2_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) &g12a_vclk2_div4_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) &g12a_vclk2_div6_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) &g12a_vclk2_div12_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) &g12a_cts_enci_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) &g12a_cts_encp_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) &g12a_cts_vdac_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) &g12a_hdmi_tx_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) &g12a_cts_enci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) &g12a_cts_encp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) &g12a_cts_vdac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) &g12a_hdmi_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) &g12a_hdmi_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) &g12a_hdmi_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) &g12a_hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) &g12a_mali_0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) &g12a_mali_0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) &g12a_mali_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) &g12a_mali_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) &g12a_mali_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) &g12a_mali_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) &g12a_mali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) &g12a_mpll_50m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) &g12a_sys_pll_div16_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) &g12a_cpu_clk_premux0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) &g12a_cpu_clk_mux0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) &g12a_cpu_clk_postmux0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) &g12a_cpu_clk_premux1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) &g12a_cpu_clk_mux1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) &g12a_cpu_clk_postmux1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) &g12a_cpu_clk_dyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) &g12a_cpu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) &g12a_cpu_clk_div16_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) &g12a_cpu_clk_apb_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) &g12a_cpu_clk_apb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) &g12a_cpu_clk_atb_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) &g12a_cpu_clk_atb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) &g12a_cpu_clk_axi_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) &g12a_cpu_clk_axi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) &g12a_cpu_clk_trace_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) &g12a_cpu_clk_trace,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) &g12a_pcie_pll_od,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) &g12a_pcie_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) &g12a_vdec_1_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) &g12a_vdec_1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) &g12a_vdec_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) &g12a_vdec_hevc_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) &g12a_vdec_hevc_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) &g12a_vdec_hevc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) &g12a_vdec_hevcf_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) &g12a_vdec_hevcf_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) &g12a_vdec_hevcf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) &g12a_ts_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) &g12a_ts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) &g12b_cpu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) &g12b_sys1_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) &g12b_sys1_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) &g12b_sys1_pll_div16_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) &g12b_cpub_clk_premux0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) &g12b_cpub_clk_mux0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) &g12b_cpub_clk_postmux0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) &g12b_cpub_clk_premux1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) &g12b_cpub_clk_mux1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) &g12b_cpub_clk_postmux1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) &g12b_cpub_clk_dyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) &g12b_cpub_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) &g12b_cpub_clk_div16_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) &g12b_cpub_clk_apb_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) &g12b_cpub_clk_apb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) &g12b_cpub_clk_atb_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) &g12b_cpub_clk_atb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) &g12b_cpub_clk_axi_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) &g12b_cpub_clk_axi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) &g12b_cpub_clk_trace_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) &g12b_cpub_clk_trace,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) &sm1_gp1_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) &sm1_gp1_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) &sm1_dsu_clk_premux0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) &sm1_dsu_clk_premux1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) &sm1_dsu_clk_mux0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) &sm1_dsu_clk_postmux0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) &sm1_dsu_clk_mux1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) &sm1_dsu_clk_postmux1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) &sm1_dsu_clk_dyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) &sm1_dsu_final_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) &sm1_dsu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) &sm1_cpu1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) &sm1_cpu2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) &sm1_cpu3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) &g12a_spicc0_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) &g12a_spicc0_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) &g12a_spicc0_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) &g12a_spicc1_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) &g12a_spicc1_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) &g12a_spicc1_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) &sm1_nna_axi_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) &sm1_nna_axi_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) &sm1_nna_axi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) &sm1_nna_core_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) &sm1_nna_core_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) &sm1_nna_core_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) static const struct reg_sequence g12a_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) #define DVFS_CON_ID "dvfs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) static int meson_g12a_dvfs_setup_common(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) struct clk_hw **hws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) struct clk *notifier_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) struct clk_hw *xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) /* Setup clock notifier for cpu_clk_postmux0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) DVFS_CON_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) ret = devm_clk_notifier_register(dev, notifier_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) &g12a_cpu_clk_postmux0_nb_data.nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) dev_err(dev, "failed to register the cpu_clk_postmux0 notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) /* Setup clock notifier for cpu_clk_dyn mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) DVFS_CON_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) ret = devm_clk_notifier_register(dev, notifier_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) &g12a_cpu_clk_mux_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) dev_err(dev, "failed to register the cpu_clk_dyn notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) static int meson_g12b_dvfs_setup(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) struct clk_hw **hws = g12b_hw_onecell_data.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) struct clk *notifier_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) struct clk_hw *xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) ret = meson_g12a_dvfs_setup_common(dev, hws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) /* Setup clock notifier for cpu_clk mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) DVFS_CON_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) ret = devm_clk_notifier_register(dev, notifier_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) &g12a_cpu_clk_mux_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) dev_err(dev, "failed to register the cpu_clk notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) /* Setup clock notifier for sys1_pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) DVFS_CON_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) ret = devm_clk_notifier_register(dev, notifier_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) &g12b_cpu_clk_sys1_pll_nb_data.nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) dev_err(dev, "failed to register the sys1_pll notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) /* Add notifiers for the second CPU cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) /* Setup clock notifier for cpub_clk_postmux0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) DVFS_CON_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) ret = devm_clk_notifier_register(dev, notifier_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) &g12b_cpub_clk_postmux0_nb_data.nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) dev_err(dev, "failed to register the cpub_clk_postmux0 notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) /* Setup clock notifier for cpub_clk_dyn mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) ret = devm_clk_notifier_register(dev, notifier_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) &g12a_cpu_clk_mux_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) dev_err(dev, "failed to register the cpub_clk_dyn notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) /* Setup clock notifier for cpub_clk mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) ret = devm_clk_notifier_register(dev, notifier_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) &g12a_cpu_clk_mux_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) dev_err(dev, "failed to register the cpub_clk notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) /* Setup clock notifier for sys_pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) ret = devm_clk_notifier_register(dev, notifier_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) &g12b_cpub_clk_sys_pll_nb_data.nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) dev_err(dev, "failed to register the sys_pll notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) static int meson_g12a_dvfs_setup(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) struct clk_hw **hws = g12a_hw_onecell_data.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) struct clk *notifier_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) ret = meson_g12a_dvfs_setup_common(dev, hws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) /* Setup clock notifier for cpu_clk mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) ret = devm_clk_notifier_register(dev, notifier_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) &g12a_cpu_clk_mux_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) dev_err(dev, "failed to register the cpu_clk notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) /* Setup clock notifier for sys_pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) ret = devm_clk_notifier_register(dev, notifier_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) &g12a_sys_pll_nb_data.nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) dev_err(dev, "failed to register the sys_pll notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) struct meson_g12a_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) const struct meson_eeclkc_data eeclkc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) int (*dvfs_setup)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) static int meson_g12a_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) const struct meson_eeclkc_data *eeclkc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) const struct meson_g12a_data *g12a_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) eeclkc_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) if (!eeclkc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) ret = meson_eeclkc_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) eeclkc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) if (g12a_data->dvfs_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) return g12a_data->dvfs_setup(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) static const struct meson_g12a_data g12a_clkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) .eeclkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) .regmap_clks = g12a_clk_regmaps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) .hw_onecell_data = &g12a_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) .init_regs = g12a_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) .init_count = ARRAY_SIZE(g12a_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) .dvfs_setup = meson_g12a_dvfs_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) static const struct meson_g12a_data g12b_clkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) .eeclkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) .regmap_clks = g12a_clk_regmaps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) .hw_onecell_data = &g12b_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) .dvfs_setup = meson_g12b_dvfs_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) static const struct meson_g12a_data sm1_clkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) .eeclkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) .regmap_clks = g12a_clk_regmaps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) .hw_onecell_data = &sm1_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) .dvfs_setup = meson_g12a_dvfs_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) static const struct of_device_id clkc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) .compatible = "amlogic,g12a-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) .data = &g12a_clkc_data.eeclkc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) .compatible = "amlogic,g12b-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) .data = &g12b_clkc_data.eeclkc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) .compatible = "amlogic,sm1-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) .data = &sm1_clkc_data.eeclkc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) MODULE_DEVICE_TABLE(of, clkc_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) static struct platform_driver g12a_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) .probe = meson_g12a_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) .name = "g12a-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) .of_match_table = clkc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) module_platform_driver(g12a_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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