^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) set ^= enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) set ? BIT(gate->bit_idx) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int clk_regmap_gate_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return clk_regmap_gate_endisable(hw, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void clk_regmap_gate_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) clk_regmap_gate_endisable(hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int clk_regmap_gate_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) regmap_read(clk->map, gate->offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (gate->flags & CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) val ^= BIT(gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) val &= BIT(gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return val ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const struct clk_ops clk_regmap_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .enable = clk_regmap_gate_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .disable = clk_regmap_gate_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .is_enabled = clk_regmap_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) EXPORT_SYMBOL_GPL(clk_regmap_gate_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const struct clk_ops clk_regmap_gate_ro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .is_enabled = clk_regmap_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) EXPORT_SYMBOL_GPL(clk_regmap_gate_ro_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ret = regmap_read(clk->map, div->offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Gives a hint that something is wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) val >>= div->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val &= clk_div_mask(div->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return divider_recalc_rate(hw, prate, val, div->table, div->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) div->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* if read only, just return current value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (div->flags & CLK_DIVIDER_READ_ONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = regmap_read(clk->map, div->offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Gives a hint that something is wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val >>= div->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val &= clk_div_mask(div->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return divider_ro_round_rate(hw, rate, prate, div->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) div->width, div->flags, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return divider_round_rate(hw, rate, prate, div->table, div->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) div->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = divider_get_val(rate, parent_rate, div->table, div->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) div->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val = (unsigned int)ret << div->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return regmap_update_bits(clk->map, div->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clk_div_mask(div->width) << div->shift, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Would prefer clk_regmap_div_ro_ops but clashes with qcom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const struct clk_ops clk_regmap_divider_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .recalc_rate = clk_regmap_div_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .round_rate = clk_regmap_div_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .set_rate = clk_regmap_div_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) EXPORT_SYMBOL_GPL(clk_regmap_divider_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const struct clk_ops clk_regmap_divider_ro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .recalc_rate = clk_regmap_div_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .round_rate = clk_regmap_div_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static u8 clk_regmap_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = regmap_read(clk->map, mux->offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val >>= mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val &= mux->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int val = clk_mux_index_to_val(mux->table, mux->flags, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return regmap_update_bits(clk->map, mux->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mux->mask << mux->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val << mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int clk_regmap_mux_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return clk_mux_determine_rate_flags(hw, req, mux->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const struct clk_ops clk_regmap_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .get_parent = clk_regmap_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .set_parent = clk_regmap_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .determine_rate = clk_regmap_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) EXPORT_SYMBOL_GPL(clk_regmap_mux_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const struct clk_ops clk_regmap_mux_ro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .get_parent = clk_regmap_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) EXPORT_SYMBOL_GPL(clk_regmap_mux_ro_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MODULE_DESCRIPTION("Amlogic regmap backed clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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