Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2015 Endless Mobile, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Carlo Caione <carlo@endlessm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2018 Baylibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * In the most basic form, a Meson PLL is composed as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *                     PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *        +--------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *        |                                |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *        |             +--+               |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *  in >>-----[ /N ]--->|  |      +-----+  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *        |             |  |------| DCO |---->> out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *        |  +--------->|  |      +--v--+  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *        |  |          +--+         |     |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *        |  |                       |     |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *        |  +--[ *(M + (F/Fmax) ]<--+     |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *        |                                |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *        +--------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * out = in * (m + frac / frac_max) / n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/rational.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static inline struct meson_clk_pll_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) meson_clk_pll_data(struct clk_regmap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	return (struct meson_clk_pll_data *)clk->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static int __pll_round_closest_mult(struct meson_clk_pll_data *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	    !MESON_PARM_APPLICABLE(&pll->frac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static unsigned long __pll_params_to_rate(unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 					  unsigned int m, unsigned int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 					  unsigned int frac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 					  struct meson_clk_pll_data *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u64 rate = (u64)parent_rate * m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		u64 frac_rate = (u64)parent_rate * frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		rate += DIV_ROUND_UP_ULL(frac_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 					 (1 << pll->frac.width));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return DIV_ROUND_UP_ULL(rate, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 						unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	unsigned int m, n, frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	n = meson_parm_read(clk->map, &pll->n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 * On some HW, N is set to zero on init. This value is invalid as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 * it would result in a division by zero. The rate can't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * calculated in this case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (n == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	m = meson_parm_read(clk->map, &pll->m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	frac = MESON_PARM_APPLICABLE(&pll->frac) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		meson_parm_read(clk->map, &pll->frac) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return __pll_params_to_rate(parent_rate, m, n, frac, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static unsigned int __pll_params_with_frac(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 					   unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 					   unsigned int m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 					   unsigned int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 					   struct meson_clk_pll_data *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned int frac_max = (1 << pll->frac.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u64 val = (u64)rate * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* Bail out if we are already over the requested rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (rate < parent_rate * m / n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		val = div_u64(val * frac_max, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	val -= m * frac_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return min((unsigned int)val, (frac_max - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static bool meson_clk_pll_is_better(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				    unsigned long best,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				    unsigned long now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				    struct meson_clk_pll_data *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (__pll_round_closest_mult(pll)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		/* Round Closest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		if (abs(now - rate) < abs(best - rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		/* Round down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		if (now <= rate && best < now)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int meson_clk_get_pll_table_index(unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 					 unsigned int *m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 					 unsigned int *n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 					 struct meson_clk_pll_data *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (!pll->table[index].n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	*m = pll->table[index].m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	*n = pll->table[index].n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static unsigned int meson_clk_get_pll_range_m(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 					      unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 					      unsigned int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 					      struct meson_clk_pll_data *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u64 val = (u64)rate * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (__pll_round_closest_mult(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return DIV_ROUND_CLOSEST_ULL(val, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return div_u64(val,  parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int meson_clk_get_pll_range_index(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 					 unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 					 unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					 unsigned int *m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 					 unsigned int *n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 					 struct meson_clk_pll_data *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	*n = index + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* Check the predivider range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (*n >= (1 << pll->n.width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (*n == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		/* Get the boundaries out the way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (rate <= pll->range->min * parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			*m = pll->range->min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		} else if (rate >= pll->range->max * parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			*m = pll->range->max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	*m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* the pre-divider gives a multiplier too big - stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (*m >= (1 << pll->m.width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int meson_clk_get_pll_get_index(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				       unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				       unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				       unsigned int *m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				       unsigned int *n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				       struct meson_clk_pll_data *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (pll->range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return meson_clk_get_pll_range_index(rate, parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 						     index, m, n, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	else if (pll->table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		return meson_clk_get_pll_table_index(index, m, n, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int meson_clk_get_pll_settings(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				      unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				      unsigned int *best_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				      unsigned int *best_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 				      struct meson_clk_pll_data *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	unsigned long best = 0, now = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	unsigned int i, m, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	for (i = 0, ret = 0; !ret; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		ret = meson_clk_get_pll_get_index(rate, parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 						  i, &m, &n, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (ret == -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		now = __pll_params_to_rate(parent_rate, m, n, 0, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		if (meson_clk_pll_is_better(rate, best, now, pll)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			best = now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			*best_m = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			*best_n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			if (now == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return best ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				     unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	unsigned int m, n, frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	unsigned long round;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	ret = meson_clk_get_pll_settings(rate, *parent_rate, &m, &n, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return meson_clk_pll_recalc_rate(hw, *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	round = __pll_params_to_rate(*parent_rate, m, n, 0, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (!MESON_PARM_APPLICABLE(&pll->frac) || rate == round)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return round;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 * The rate provided by the setting is not an exact match, let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 * try to improve the result using the fractional parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	frac = __pll_params_with_frac(rate, *parent_rate, m, n, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return __pll_params_to_rate(*parent_rate, m, n, frac, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int meson_clk_pll_wait_lock(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	int delay = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		/* Is the clock locked now ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		if (meson_parm_read(clk->map, &pll->l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		delay--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	} while (delay > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int meson_clk_pll_init(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (pll->init_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		meson_parm_write(clk->map, &pll->rst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		regmap_multi_reg_write(clk->map, pll->init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				       pll->init_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		meson_parm_write(clk->map, &pll->rst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int meson_clk_pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (meson_parm_read(clk->map, &pll->rst) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	    !meson_parm_read(clk->map, &pll->en) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	    !meson_parm_read(clk->map, &pll->l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	meson_clk_pll_init(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (meson_clk_pll_wait_lock(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int meson_clk_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	/* do nothing if the PLL is already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (clk_hw_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* Make sure the pll is in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	meson_parm_write(clk->map, &pll->rst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	/* Enable the pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	meson_parm_write(clk->map, &pll->en, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	/* Take the pll out reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	meson_parm_write(clk->map, &pll->rst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (meson_clk_pll_wait_lock(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void meson_clk_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/* Put the pll is in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	meson_parm_write(clk->map, &pll->rst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	/* Disable the pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	meson_parm_write(clk->map, &pll->en, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 				  unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	unsigned int enabled, m, n, frac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	unsigned long old_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (parent_rate == 0 || rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	old_rate = clk_hw_get_rate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	enabled = meson_parm_read(clk->map, &pll->en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		meson_clk_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	meson_parm_write(clk->map, &pll->n, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	meson_parm_write(clk->map, &pll->m, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (MESON_PARM_APPLICABLE(&pll->frac)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		frac = __pll_params_with_frac(rate, parent_rate, m, n, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		meson_parm_write(clk->map, &pll->frac, frac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	/* If the pll is stopped, bail out now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	if (!enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	ret = meson_clk_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 			__func__, old_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		 * FIXME: Do we really need/want this HACK ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		 * It looks unsafe. what happens if the clock gets into a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		 * broken state and we can't lock back on the old_rate ? Looks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		 * like an infinite recursion is possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		meson_clk_pll_set_rate(hw, old_rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)  * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)  * 100MHz reference clock for the PCIe Analog PHY, and thus requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)  * a strict register sequence to enable the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)  * To simplify, re-use the _init() op to enable the PLL and keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)  * the other ops except set_rate since the rate is fixed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) const struct clk_ops meson_clk_pcie_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.recalc_rate	= meson_clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	.round_rate	= meson_clk_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	.is_enabled	= meson_clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	.enable		= meson_clk_pcie_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	.disable	= meson_clk_pll_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) const struct clk_ops meson_clk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	.init		= meson_clk_pll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.recalc_rate	= meson_clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.round_rate	= meson_clk_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	.set_rate	= meson_clk_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	.is_enabled	= meson_clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.enable		= meson_clk_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.disable	= meson_clk_pll_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) EXPORT_SYMBOL_GPL(meson_clk_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) const struct clk_ops meson_clk_pll_ro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.recalc_rate	= meson_clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	.is_enabled	= meson_clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) EXPORT_SYMBOL_GPL(meson_clk_pll_ro_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_DESCRIPTION("Amlogic PLL driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_LICENSE("GPL v2");