^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define phase_step(_width) (360 / (1 << (_width)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static inline struct meson_clk_phase_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) meson_clk_phase_data(struct clk_regmap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) return (struct meson_clk_phase_data *)clk->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int meson_clk_degrees_from_val(unsigned int val, unsigned int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) return phase_step(width) * val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * This last calculation is here for cases when degrees is rounded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * to 360, in which case val == (1 << width).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return val % (1 << width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int meson_clk_phase_get_phase(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) val = meson_parm_read(clk->map, &phase->ph);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return meson_clk_degrees_from_val(val, phase->ph.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) val = meson_clk_degrees_to_val(degrees, phase->ph.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) meson_parm_write(clk->map, &phase->ph, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct clk_ops meson_clk_phase_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .get_phase = meson_clk_phase_get_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .set_phase = meson_clk_phase_set_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) EXPORT_SYMBOL_GPL(meson_clk_phase_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * This is a special clock for the audio controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * The phase of mst_sclk clock output can be controlled independently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * for the outside world (ph0), the tdmout (ph1) and tdmin (ph2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Controlling these 3 phases as just one makes things simpler and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * give the same clock view to all the element on the i2s bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * If necessary, we can still control the phase in the tdm block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * which makes these independent control redundant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline struct meson_clk_triphase_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) meson_clk_triphase_data(struct clk_regmap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return (struct meson_clk_triphase_data *)clk->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int meson_clk_triphase_sync(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Get phase 0 and sync it to phase 1 and 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val = meson_parm_read(clk->map, &tph->ph0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) meson_parm_write(clk->map, &tph->ph1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) meson_parm_write(clk->map, &tph->ph2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int meson_clk_triphase_get_phase(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Phase are in sync, reading phase 0 is enough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val = meson_parm_read(clk->map, &tph->ph0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return meson_clk_degrees_from_val(val, tph->ph0.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int meson_clk_triphase_set_phase(struct clk_hw *hw, int degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val = meson_clk_degrees_to_val(degrees, tph->ph0.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) meson_parm_write(clk->map, &tph->ph0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) meson_parm_write(clk->map, &tph->ph1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) meson_parm_write(clk->map, &tph->ph2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct clk_ops meson_clk_triphase_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .init = meson_clk_triphase_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .get_phase = meson_clk_triphase_get_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .set_phase = meson_clk_triphase_set_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXPORT_SYMBOL_GPL(meson_clk_triphase_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * This is a special clock for the audio controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * This drive a bit clock inverter for which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * opposite value of the inverter bit needs to be manually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * set into another bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline struct meson_sclk_ws_inv_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) meson_sclk_ws_inv_data(struct clk_regmap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return (struct meson_sclk_ws_inv_data *)clk->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int meson_sclk_ws_inv_sync(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Get phase and sync the inverted value to ws */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val = meson_parm_read(clk->map, &tph->ph);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) meson_parm_write(clk->map, &tph->ws, val ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int meson_sclk_ws_inv_get_phase(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = meson_parm_read(clk->map, &tph->ph);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return meson_clk_degrees_from_val(val, tph->ph.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int meson_sclk_ws_inv_set_phase(struct clk_hw *hw, int degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct clk_regmap *clk = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val = meson_clk_degrees_to_val(degrees, tph->ph.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) meson_parm_write(clk->map, &tph->ph, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) meson_parm_write(clk->map, &tph->ws, val ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const struct clk_ops meson_sclk_ws_inv_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .init = meson_sclk_ws_inv_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .get_phase = meson_sclk_ws_inv_get_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .set_phase = meson_sclk_ws_inv_set_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) EXPORT_SYMBOL_GPL(meson_sclk_ws_inv_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MODULE_DESCRIPTION("Amlogic phase driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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