^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 AmLogic, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Michael Turquette <mturquette@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2017 Amlogic, inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Qiufang Dai <qiufang.dai@amlogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __AXG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __AXG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Clock controller register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Register offsets from the data sheet must be multiplied by 4 before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * adding them to the base address to get the right value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HHI_MIPI_CNTL0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HHI_GP0_PLL_CNTL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HHI_GP0_PLL_CNTL2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HHI_GP0_PLL_CNTL3 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HHI_GP0_PLL_CNTL4 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HHI_GP0_PLL_CNTL5 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HHI_GP0_PLL_STS 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HHI_GP0_PLL_CNTL1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HHI_HIFI_PLL_CNTL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HHI_HIFI_PLL_CNTL2 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HHI_HIFI_PLL_CNTL3 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HHI_HIFI_PLL_CNTL4 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HHI_HIFI_PLL_CNTL5 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HHI_HIFI_PLL_STS 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HHI_HIFI_PLL_CNTL1 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HHI_XTAL_DIVN_CNTL 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HHI_GCLK2_MPEG0 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HHI_GCLK2_MPEG1 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HHI_GCLK2_MPEG2 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HHI_GCLK2_OTHER 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HHI_GCLK2_AO 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HHI_PCIE_PLL_CNTL 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HHI_PCIE_PLL_CNTL1 0xdC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HHI_PCIE_PLL_CNTL2 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HHI_PCIE_PLL_CNTL3 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HHI_PCIE_PLL_CNTL4 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HHI_PCIE_PLL_CNTL5 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HHI_PCIE_PLL_CNTL6 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HHI_PCIE_PLL_STS 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HHI_MEM_PD_REG0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HHI_VPU_MEM_PD_REG0 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HHI_VIID_CLK_DIV 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HHI_VIID_CLK_CNTL 0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HHI_GCLK_MPEG0 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HHI_GCLK_MPEG1 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HHI_GCLK_MPEG2 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HHI_GCLK_OTHER 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HHI_GCLK_AO 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HHI_SYS_CPU_CLK_CNTL1 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HHI_SYS_CPU_RESET_CNTL 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HHI_VID_CLK_DIV 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HHI_SPICC_HCLK_CNTL 0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HHI_MPEG_CLK_CNTL 0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HHI_VID_CLK_CNTL 0x17c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HHI_TS_CLK_CNTL 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HHI_VID_CLK_CNTL2 0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HHI_SYS_CPU_CLK_CNTL0 0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HHI_VID_PLL_CLK_DIV 0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HHI_VPU_CLK_CNTL 0x1bC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HHI_VAPBCLK_CNTL 0x1F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HHI_GEN_CLK_CNTL 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HHI_VDIN_MEAS_CLK_CNTL 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HHI_NAND_CLK_CNTL 0x25C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HHI_SD_EMMC_CLK_CNTL 0x264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HHI_MPLL_CNTL 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HHI_MPLL_CNTL2 0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HHI_MPLL_CNTL3 0x288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HHI_MPLL_CNTL4 0x28C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HHI_MPLL_CNTL5 0x290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HHI_MPLL_CNTL6 0x294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HHI_MPLL_CNTL7 0x298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HHI_MPLL_CNTL8 0x29C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HHI_MPLL_CNTL9 0x2A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HHI_MPLL_CNTL10 0x2A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HHI_MPLL3_CNTL0 0x2E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HHI_MPLL3_CNTL1 0x2E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HHI_PLL_TOP_MISC 0x2E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HHI_SYS_PLL_CNTL1 0x2FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HHI_SYS_PLL_CNTL 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HHI_SYS_PLL_CNTL2 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HHI_SYS_PLL_CNTL3 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HHI_SYS_PLL_CNTL4 0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HHI_SYS_PLL_CNTL5 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HHI_SYS_PLL_STS 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HHI_DPLL_TOP_I 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HHI_DPLL_TOP2_I 0x31C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * CLKID index values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * These indices are entirely contrived and do not map onto the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * It has now been decided to expose everything by default in the DT header:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * to expose, such as the internal muxes and dividers of composite clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * will remain defined here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLKID_MPEG_SEL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLKID_MPEG_DIV 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLKID_SD_EMMC_B_CLK0_SEL 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLKID_SD_EMMC_B_CLK0_DIV 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLKID_SD_EMMC_C_CLK0_SEL 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLKID_SD_EMMC_C_CLK0_DIV 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLKID_MPLL0_DIV 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLKID_MPLL1_DIV 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLKID_MPLL2_DIV 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLKID_MPLL3_DIV 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLKID_MPLL_PREDIV 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLKID_FCLK_DIV2_DIV 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLKID_FCLK_DIV3_DIV 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLKID_FCLK_DIV4_DIV 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLKID_FCLK_DIV5_DIV 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLKID_FCLK_DIV7_DIV 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLKID_PCIE_PLL 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLKID_PCIE_MUX 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLKID_PCIE_REF 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLKID_GEN_CLK_SEL 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLKID_GEN_CLK_DIV 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLKID_SYS_PLL_DCO 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLKID_FIXED_PLL_DCO 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLKID_GP0_PLL_DCO 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLKID_HIFI_PLL_DCO 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLKID_PCIE_PLL_DCO 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLKID_PCIE_PLL_OD 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define NR_CLKS 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* include the CLKIDs that have been made part of the DT binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #include <dt-bindings/clock/axg-clkc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif /* __AXG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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