^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AmLogic Meson-AXG Clock Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Baylibre SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Michael Turquette <mturquette@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2017 Amlogic, inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Qiufang Dai <qiufang.dai@amlogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-mpll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "axg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "meson-eeclk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static DEFINE_SPINLOCK(meson_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct clk_regmap axg_fixed_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .reg_off = HHI_MPLL_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .name = "fixed_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct clk_regmap axg_fixed_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .offset = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .name = "fixed_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) &axg_fixed_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * This clock won't ever change at runtime so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * CLK_SET_RATE_PARENT is not required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct clk_regmap axg_sys_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .reg_off = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "sys_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .ops = &meson_clk_pll_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct clk_regmap axg_sys_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .offset = HHI_SYS_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .name = "sys_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) &axg_sys_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct pll_params_table axg_gp0_pll_params_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PLL_PARAMS(40, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PLL_PARAMS(41, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PLL_PARAMS(42, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PLL_PARAMS(43, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PLL_PARAMS(44, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PLL_PARAMS(45, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PLL_PARAMS(46, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PLL_PARAMS(47, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PLL_PARAMS(48, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PLL_PARAMS(49, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PLL_PARAMS(50, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PLL_PARAMS(51, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PLL_PARAMS(52, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PLL_PARAMS(53, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PLL_PARAMS(54, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PLL_PARAMS(55, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PLL_PARAMS(56, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PLL_PARAMS(57, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PLL_PARAMS(58, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PLL_PARAMS(59, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PLL_PARAMS(60, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PLL_PARAMS(61, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PLL_PARAMS(62, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PLL_PARAMS(63, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PLL_PARAMS(64, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PLL_PARAMS(65, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PLL_PARAMS(66, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PLL_PARAMS(67, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PLL_PARAMS(68, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct reg_sequence axg_gp0_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct clk_regmap axg_gp0_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .reg_off = HHI_GP0_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .width = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .reg_off = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .table = axg_gp0_pll_params_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .init_regs = axg_gp0_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .init_count = ARRAY_SIZE(axg_gp0_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .name = "gp0_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct clk_regmap axg_gp0_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .offset = HHI_GP0_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "gp0_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) &axg_gp0_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct reg_sequence axg_hifi_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct clk_regmap axg_hifi_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .reg_off = HHI_HIFI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .reg_off = HHI_HIFI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .reg_off = HHI_HIFI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .reg_off = HHI_HIFI_PLL_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .width = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .reg_off = HHI_HIFI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .reg_off = HHI_HIFI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .table = axg_gp0_pll_params_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .init_regs = axg_hifi_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .init_count = ARRAY_SIZE(axg_hifi_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .flags = CLK_MESON_PLL_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .name = "hifi_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct clk_regmap axg_hifi_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .offset = HHI_HIFI_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = "hifi_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) &axg_hifi_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct clk_fixed_factor axg_fclk_div2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .name = "fclk_div2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct clk_regmap axg_fclk_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .bit_idx = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .name = "fclk_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) &axg_fclk_div2_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct clk_fixed_factor axg_fclk_div3_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .div = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .name = "fclk_div3_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct clk_regmap axg_fclk_div3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .bit_idx = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .name = "fclk_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) &axg_fclk_div3_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * FIXME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * This clock, as fdiv2, is used by the SCPI FW and is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * by the platform to operate correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Until the following condition are met, we need this clock to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * be marked as critical:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * a) The SCPI generic driver claims and enable all the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * it needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * b) CCF has a clock hand-off mechanism to make the sure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * clock stays on until the proper driver comes along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct clk_fixed_factor axg_fclk_div4_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .name = "fclk_div4_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct clk_regmap axg_fclk_div4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .bit_idx = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "fclk_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) &axg_fclk_div4_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct clk_fixed_factor axg_fclk_div5_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .div = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .name = "fclk_div5_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct clk_regmap axg_fclk_div5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .bit_idx = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .name = "fclk_div5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) &axg_fclk_div5_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static struct clk_fixed_factor axg_fclk_div7_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .div = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .name = "fclk_div7_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) &axg_fixed_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct clk_regmap axg_fclk_div7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .offset = HHI_MPLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .bit_idx = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .name = "fclk_div7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) &axg_fclk_div7_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct clk_regmap axg_mpll_prediv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .offset = HHI_MPLL_CNTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .name = "mpll_prediv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .ops = &clk_regmap_divider_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) &axg_fixed_pll.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct clk_regmap axg_mpll0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .reg_off = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .misc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .reg_off = HHI_PLL_TOP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .name = "mpll0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) &axg_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static struct clk_regmap axg_mpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .offset = HHI_MPLL_CNTL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .bit_idx = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .name = "mpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &axg_mpll0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static struct clk_regmap axg_mpll1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .reg_off = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .reg_off = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .reg_off = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .misc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .reg_off = HHI_PLL_TOP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .name = "mpll1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) &axg_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static struct clk_regmap axg_mpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .offset = HHI_MPLL_CNTL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .bit_idx = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = "mpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) &axg_mpll1_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct clk_regmap axg_mpll2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .reg_off = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .reg_off = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .reg_off = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .ssen = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .reg_off = HHI_MPLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .misc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .reg_off = HHI_PLL_TOP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .name = "mpll2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) &axg_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static struct clk_regmap axg_mpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .offset = HHI_MPLL_CNTL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .bit_idx = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .name = "mpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) &axg_mpll2_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static struct clk_regmap axg_mpll3_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .data = &(struct meson_clk_mpll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .sdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .reg_off = HHI_MPLL3_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .width = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .sdm_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .reg_off = HHI_MPLL3_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .reg_off = HHI_MPLL3_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .misc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .reg_off = HHI_PLL_TOP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .lock = &meson_clk_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .name = "mpll3_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .ops = &meson_clk_mpll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) &axg_mpll_prediv.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static struct clk_regmap axg_mpll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .offset = HHI_MPLL3_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .bit_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .name = "mpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) &axg_mpll3_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static const struct pll_params_table axg_pcie_pll_params_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .m = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .n = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const struct reg_sequence axg_pcie_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static struct clk_regmap axg_pcie_pll_dco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .data = &(struct meson_clk_pll_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .reg_off = HHI_PCIE_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .m = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .reg_off = HHI_PCIE_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .width = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .reg_off = HHI_PCIE_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .reg_off = HHI_PCIE_PLL_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .l = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .reg_off = HHI_PCIE_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .rst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .reg_off = HHI_PCIE_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .table = axg_pcie_pll_params_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .init_regs = axg_pcie_init_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .init_count = ARRAY_SIZE(axg_pcie_init_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .name = "pcie_pll_dco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .ops = &meson_clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static struct clk_regmap axg_pcie_pll_od = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .offset = HHI_PCIE_PLL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .name = "pcie_pll_od",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) &axg_pcie_pll_dco.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static struct clk_regmap axg_pcie_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .offset = HHI_PCIE_PLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .name = "pcie_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) &axg_pcie_pll_od.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static struct clk_regmap axg_pcie_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .offset = HHI_PCIE_PLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* skip the parent mpll3, reserved for debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .table = (u32[]){ 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .name = "pcie_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static struct clk_regmap axg_pcie_ref = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .offset = HHI_PCIE_PLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* skip the parent 0, reserved for debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .table = (u32[]){ 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .name = "pcie_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static struct clk_regmap axg_pcie_cml_en0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .offset = HHI_PCIE_PLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .bit_idx = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .name = "pcie_cml_en0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static struct clk_regmap axg_pcie_cml_en1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .offset = HHI_PCIE_PLL_CNTL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .bit_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .name = "pcie_cml_en1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static const struct clk_parent_data clk81_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) { .hw = &axg_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) { .hw = &axg_mpll1.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) { .hw = &axg_mpll2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) { .hw = &axg_fclk_div4.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) { .hw = &axg_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { .hw = &axg_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static struct clk_regmap axg_mpeg_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .table = mux_table_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .name = "mpeg_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .parent_data = clk81_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .num_parents = ARRAY_SIZE(clk81_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static struct clk_regmap axg_mpeg_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .name = "mpeg_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) &axg_mpeg_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static struct clk_regmap axg_clk81 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .offset = HHI_MPEG_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .name = "clk81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) &axg_mpeg_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) { .hw = &axg_fclk_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) { .hw = &axg_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) { .hw = &axg_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) { .hw = &axg_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * Following these parent clocks, we should also have had mpll2, mpll3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * and gp0_pll but these clocks are too precious to be used here. All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * the necessary rates for MMC and NAND operation can be acheived using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * xtal or fclk_div clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* SDcard clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .shift = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .name = "sd_emmc_b_clk0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .parent_data = axg_sd_emmc_clk0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static struct clk_regmap axg_sd_emmc_b_clk0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .name = "sd_emmc_b_clk0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) &axg_sd_emmc_b_clk0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static struct clk_regmap axg_sd_emmc_b_clk0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .offset = HHI_SD_EMMC_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .bit_idx = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .name = "sd_emmc_b_clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) &axg_sd_emmc_b_clk0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* EMMC/NAND clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .name = "sd_emmc_c_clk0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .parent_data = axg_sd_emmc_clk0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static struct clk_regmap axg_sd_emmc_c_clk0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .width = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .flags = CLK_DIVIDER_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .name = "sd_emmc_c_clk0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) &axg_sd_emmc_c_clk0_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static struct clk_regmap axg_sd_emmc_c_clk0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .offset = HHI_NAND_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .name = "sd_emmc_c_clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) &axg_sd_emmc_c_clk0_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) 9, 10, 11, 13, 14, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static const struct clk_parent_data gen_clk_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) { .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) { .hw = &axg_hifi_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) { .hw = &axg_mpll0.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) { .hw = &axg_mpll1.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) { .hw = &axg_mpll2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) { .hw = &axg_mpll3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) { .hw = &axg_fclk_div4.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) { .hw = &axg_fclk_div3.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) { .hw = &axg_fclk_div5.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) { .hw = &axg_fclk_div7.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) { .hw = &axg_gp0_pll.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static struct clk_regmap axg_gen_clk_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .offset = HHI_GEN_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .table = mux_table_gen_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .name = "gen_clk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * bits 15:12 selects from 14 possible parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .parent_data = gen_clk_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .num_parents = ARRAY_SIZE(gen_clk_parent_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static struct clk_regmap axg_gen_clk_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .offset = HHI_GEN_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .width = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .name = "gen_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) &axg_gen_clk_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static struct clk_regmap axg_gen_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .offset = HHI_GEN_CLK_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .bit_idx = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .name = "gen_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) &axg_gen_clk_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define MESON_GATE(_name, _reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Everything Else (EE) domain gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Always On (AO) domain gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Array of all clocks provided by this provider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static struct clk_hw_onecell_data axg_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) [CLKID_SYS_PLL] = &axg_sys_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) [CLKID_CLK81] = &axg_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) [CLKID_MPLL0] = &axg_mpll0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) [CLKID_MPLL1] = &axg_mpll1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) [CLKID_MPLL2] = &axg_mpll2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) [CLKID_MPLL3] = &axg_mpll3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) [CLKID_DDR] = &axg_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) [CLKID_ISA] = &axg_isa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) [CLKID_PL301] = &axg_pl301.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) [CLKID_PERIPHS] = &axg_periphs.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) [CLKID_SPICC0] = &axg_spicc_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) [CLKID_I2C] = &axg_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) [CLKID_RNG0] = &axg_rng0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) [CLKID_UART0] = &axg_uart0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) [CLKID_SPICC1] = &axg_spicc_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) [CLKID_PCIE_A] = &axg_pcie_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) [CLKID_PCIE_B] = &axg_pcie_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) [CLKID_DMA] = &axg_dma.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) [CLKID_SPI] = &axg_spi.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) [CLKID_AUDIO] = &axg_audio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) [CLKID_ETH] = &axg_eth_core.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) [CLKID_UART1] = &axg_uart1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) [CLKID_G2D] = &axg_g2d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) [CLKID_USB0] = &axg_usb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) [CLKID_USB1] = &axg_usb1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) [CLKID_RESET] = &axg_reset.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) [CLKID_USB] = &axg_usb_general.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) [CLKID_EFUSE] = &axg_efuse.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) [CLKID_GIC] = &axg_gic.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) [CLKID_AO_IFACE] = &axg_ao_iface.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) [CLKID_AO_I2C] = &axg_ao_i2c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) [CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) [CLKID_GEN_CLK] = &axg_gen_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) [NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* Convenience table to populate regmap in .probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static struct clk_regmap *const axg_clk_regmaps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) &axg_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) &axg_ddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) &axg_audio_locker,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) &axg_mipi_dsi_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) &axg_isa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) &axg_pl301,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) &axg_periphs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) &axg_spicc_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) &axg_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) &axg_rng0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) &axg_uart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) &axg_mipi_dsi_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) &axg_spicc_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) &axg_pcie_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) &axg_pcie_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) &axg_hiu_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) &axg_assist_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) &axg_emmc_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) &axg_emmc_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) &axg_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) &axg_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) &axg_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) &axg_eth_core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) &axg_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) &axg_g2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) &axg_usb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) &axg_usb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) &axg_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) &axg_usb_general,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) &axg_ahb_arb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) &axg_efuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) &axg_boot_rom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) &axg_ahb_data_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) &axg_ahb_ctrl_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) &axg_usb1_to_ddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) &axg_usb0_to_ddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) &axg_mmc_pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) &axg_vpu_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) &axg_sec_ahb_ahb3_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) &axg_gic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) &axg_ao_media_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) &axg_ao_ahb_sram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) &axg_ao_ahb_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) &axg_ao_iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) &axg_ao_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) &axg_sd_emmc_b_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) &axg_sd_emmc_c_clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) &axg_mpeg_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) &axg_sd_emmc_b_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) &axg_sd_emmc_c_clk0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) &axg_mpeg_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) &axg_sd_emmc_b_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) &axg_sd_emmc_c_clk0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) &axg_mpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) &axg_mpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) &axg_mpll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) &axg_mpll3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) &axg_mpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) &axg_mpll1_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) &axg_mpll2_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) &axg_mpll3_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) &axg_fixed_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) &axg_sys_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) &axg_gp0_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) &axg_hifi_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) &axg_mpll_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) &axg_fclk_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) &axg_fclk_div3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) &axg_fclk_div4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) &axg_fclk_div5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) &axg_fclk_div7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) &axg_pcie_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) &axg_pcie_pll_od,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) &axg_pcie_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &axg_pcie_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) &axg_pcie_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) &axg_pcie_cml_en0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) &axg_pcie_cml_en1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) &axg_mipi_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) &axg_gen_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) &axg_gen_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) &axg_gen_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) &axg_fixed_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) &axg_sys_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) &axg_gp0_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) &axg_hifi_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) &axg_pcie_pll_dco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) &axg_pcie_pll_od,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static const struct meson_eeclkc_data axg_clkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .regmap_clks = axg_clk_regmaps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .hw_onecell_data = &axg_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static const struct of_device_id clkc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) MODULE_DEVICE_TABLE(of, clkc_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static struct platform_driver axg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .probe = meson_eeclkc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .name = "axg-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .of_match_table = clkc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) module_platform_driver(axg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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