^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __AXG_AUDIO_CLKC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __AXG_AUDIO_CLKC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Audio Clock register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Register offsets from the datasheet must be multiplied by 4 before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * to get the right offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AUDIO_CLK_GATE_EN 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AUDIO_MCLK_A_CTRL 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AUDIO_MCLK_B_CTRL 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AUDIO_MCLK_C_CTRL 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AUDIO_MCLK_D_CTRL 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AUDIO_MCLK_E_CTRL 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AUDIO_MCLK_F_CTRL 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AUDIO_MST_PAD_CTRL0 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AUDIO_MST_PAD_CTRL1 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AUDIO_SW_RESET 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AUDIO_MST_A_SCLK_CTRL0 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AUDIO_MST_A_SCLK_CTRL1 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AUDIO_MST_B_SCLK_CTRL0 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AUDIO_MST_B_SCLK_CTRL1 0x04C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AUDIO_MST_C_SCLK_CTRL0 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AUDIO_MST_C_SCLK_CTRL1 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AUDIO_MST_D_SCLK_CTRL0 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AUDIO_MST_D_SCLK_CTRL1 0x05C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AUDIO_MST_E_SCLK_CTRL0 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AUDIO_MST_E_SCLK_CTRL1 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AUDIO_MST_F_SCLK_CTRL0 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AUDIO_MST_F_SCLK_CTRL1 0x06C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AUDIO_CLK_TDMIN_A_CTRL 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AUDIO_CLK_TDMIN_B_CTRL 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AUDIO_CLK_TDMIN_C_CTRL 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AUDIO_CLK_TDMOUT_A_CTRL 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AUDIO_CLK_TDMOUT_B_CTRL 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AUDIO_CLK_TDMOUT_C_CTRL 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AUDIO_CLK_SPDIFIN_CTRL 0x09C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AUDIO_CLK_LOCKER_CTRL 0x0A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AUDIO_CLK_PDMIN_CTRL0 0x0AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AUDIO_CLK_PDMIN_CTRL1 0x0B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* SM1 introduce new register and some shifts :( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AUDIO_CLK_GATE_EN1 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AUDIO_SM1_MCLK_A_CTRL 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AUDIO_SM1_MCLK_B_CTRL 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AUDIO_SM1_MCLK_C_CTRL 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AUDIO_SM1_MCLK_D_CTRL 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AUDIO_SM1_MCLK_E_CTRL 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AUDIO_SM1_MCLK_F_CTRL 0x01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AUDIO_SM1_MST_PAD_CTRL0 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AUDIO_SM1_MST_PAD_CTRL1 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AUDIO_SM1_SW_RESET0 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AUDIO_SM1_SW_RESET1 0x02C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AUDIO_CLK81_CTRL 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AUDIO_CLK81_EN 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * CLKID index values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * These indices are entirely contrived and do not map onto the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AUD_CLKID_MST_A_MCLK_SEL 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AUD_CLKID_MST_B_MCLK_SEL 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AUD_CLKID_MST_C_MCLK_SEL 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AUD_CLKID_MST_D_MCLK_SEL 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AUD_CLKID_MST_E_MCLK_SEL 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AUD_CLKID_MST_F_MCLK_SEL 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AUD_CLKID_MST_A_MCLK_DIV 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AUD_CLKID_MST_B_MCLK_DIV 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AUD_CLKID_MST_C_MCLK_DIV 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AUD_CLKID_MST_D_MCLK_DIV 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AUD_CLKID_MST_E_MCLK_DIV 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AUD_CLKID_MST_F_MCLK_DIV 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AUD_CLKID_SPDIFOUT_CLK_SEL 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AUD_CLKID_SPDIFOUT_CLK_DIV 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AUD_CLKID_SPDIFIN_CLK_SEL 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AUD_CLKID_SPDIFIN_CLK_DIV 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AUD_CLKID_PDM_DCLK_SEL 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AUD_CLKID_PDM_DCLK_DIV 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AUD_CLKID_PDM_SYSCLK_SEL 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AUD_CLKID_PDM_SYSCLK_DIV 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AUD_CLKID_MST_A_SCLK_PRE_EN 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AUD_CLKID_MST_B_SCLK_PRE_EN 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AUD_CLKID_MST_C_SCLK_PRE_EN 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AUD_CLKID_MST_D_SCLK_PRE_EN 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AUD_CLKID_MST_E_SCLK_PRE_EN 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AUD_CLKID_MST_F_SCLK_PRE_EN 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AUD_CLKID_MST_A_SCLK_DIV 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AUD_CLKID_MST_B_SCLK_DIV 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AUD_CLKID_MST_C_SCLK_DIV 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AUD_CLKID_MST_D_SCLK_DIV 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AUD_CLKID_MST_E_SCLK_DIV 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AUD_CLKID_MST_F_SCLK_DIV 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AUD_CLKID_MST_A_SCLK_POST_EN 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AUD_CLKID_MST_B_SCLK_POST_EN 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AUD_CLKID_MST_C_SCLK_POST_EN 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AUD_CLKID_MST_D_SCLK_POST_EN 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AUD_CLKID_MST_E_SCLK_POST_EN 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AUD_CLKID_MST_F_SCLK_POST_EN 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AUD_CLKID_MST_A_LRCLK_DIV 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AUD_CLKID_MST_B_LRCLK_DIV 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AUD_CLKID_MST_C_LRCLK_DIV 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AUD_CLKID_MST_D_LRCLK_DIV 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AUD_CLKID_MST_E_LRCLK_DIV 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AUD_CLKID_MST_F_LRCLK_DIV 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AUD_CLKID_CLK81_EN 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AUD_CLKID_SYSCLK_A_DIV 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AUD_CLKID_SYSCLK_B_DIV 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AUD_CLKID_SYSCLK_A_EN 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AUD_CLKID_SYSCLK_B_EN 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* include the CLKIDs which are part of the DT bindings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #include <dt-bindings/clock/axg-audio-clkc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define NR_CLKS 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif /*__AXG_AUDIO_CLKC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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