^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "axg-audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "sclk-div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .data = &(struct clk_regmap_gate_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .offset = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .bit_idx = (_bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = "aud_"#_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .ops = &clk_regmap_gate_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .parent_names = (const char *[]){ #_pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .data = &(struct clk_regmap_mux_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .offset = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .mask = (_mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .shift = (_shift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .flags = (_dflags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .name = "aud_"#_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .ops = &clk_regmap_mux_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .parent_data = _pdata, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .num_parents = ARRAY_SIZE(_pdata), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .data = &(struct clk_regmap_div_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .offset = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .shift = (_shift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .width = (_width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .flags = (_dflags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "aud_"#_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .ops = &clk_regmap_divider_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .parent_names = (const char *[]){ #_pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .flags = (_iflags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AUD_PCLK_GATE(_name, _reg, _bit) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .data = &(struct clk_regmap_gate_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .offset = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .bit_idx = (_bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "aud_"#_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .ops = &clk_regmap_gate_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .parent_names = (const char *[]){ "aud_top" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) _hi_shift, _hi_width, _pname, _iflags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .data = &(struct meson_sclk_div_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .div = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .reg_off = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .shift = (_div_shift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .width = (_div_width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .hi = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .reg_off = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .shift = (_hi_shift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .width = (_hi_width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .name = "aud_"#_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .ops = &meson_sclk_div_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .parent_names = (const char *[]){ #_pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .flags = (_iflags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) _pname, _iflags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .data = &(struct meson_clk_triphase_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .ph0 = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .reg_off = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .shift = (_shift0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .width = (_width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .ph1 = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .reg_off = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .shift = (_shift1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .width = (_width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .ph2 = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .reg_off = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .shift = (_shift2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .width = (_width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .name = "aud_"#_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .ops = &meson_clk_triphase_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .parent_names = (const char *[]){ #_pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .data = &(struct meson_clk_phase_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .ph = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .reg_off = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .shift = (_shift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .width = (_width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = "aud_"#_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .ops = &meson_clk_phase_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .parent_names = (const char *[]){ #_pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .flags = (_iflags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) _iflags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .data = &(struct meson_sclk_ws_inv_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .ph = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .reg_off = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .shift = (_shift_ph), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .width = (_width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .ws = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .reg_off = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .shift = (_shift_ws), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .width = (_width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "aud_"#_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .ops = &meson_clk_phase_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .parent_names = (const char *[]){ #_pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .flags = (_iflags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Audio Master Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct clk_parent_data mst_mux_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .fw_name = "mst_in0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .fw_name = "mst_in1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { .fw_name = "mst_in2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .fw_name = "mst_in3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .fw_name = "mst_in4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .fw_name = "mst_in5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .fw_name = "mst_in6", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .fw_name = "mst_in7", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AUD_MST_MUX(_name, _reg, _flag) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mst_mux_parent_data, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AUD_MST_DIV(_name, _reg, _flag) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) aud_##_name##_sel, CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AUD_MST_MCLK_GATE(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) AUD_GATE(_name, _reg, 31, aud_##_name##_div, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AUD_MST_MCLK_MUX(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AUD_MST_MCLK_DIV(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AUD_MST_SYS_MUX(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) AUD_MST_MUX(_name, _reg, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AUD_MST_SYS_DIV(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) AUD_MST_DIV(_name, _reg, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Sample Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AUD_MST_SCLK_PRE_EN(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) aud_mst_##_name##_mclk, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AUD_MST_SCLK_DIV(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) aud_mst_##_name##_sclk_pre_en, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AUD_MST_SCLK_POST_EN(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AUD_MST_SCLK(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AUD_MST_LRCLK_DIV(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) aud_mst_##_name##_sclk_post_en, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AUD_MST_LRCLK(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* TDM bit clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct clk_parent_data tdm_sclk_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { .name = "aud_mst_a_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { .name = "aud_mst_b_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { .name = "aud_mst_c_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { .name = "aud_mst_d_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { .name = "aud_mst_e_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { .name = "aud_mst_f_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { .fw_name = "slv_sclk0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { .fw_name = "slv_sclk1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { .fw_name = "slv_sclk2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { .fw_name = "slv_sclk3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { .fw_name = "slv_sclk4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { .fw_name = "slv_sclk5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .fw_name = "slv_sclk6", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .fw_name = "slv_sclk7", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .fw_name = "slv_sclk8", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .fw_name = "slv_sclk9", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* TDM sample clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct clk_parent_data tdm_lrclk_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { .name = "aud_mst_a_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { .name = "aud_mst_b_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { .name = "aud_mst_c_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .name = "aud_mst_d_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .name = "aud_mst_e_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .name = "aud_mst_f_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .fw_name = "slv_lrclk0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { .fw_name = "slv_lrclk1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { .fw_name = "slv_lrclk2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { .fw_name = "slv_lrclk3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { .fw_name = "slv_lrclk4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { .fw_name = "slv_lrclk5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { .fw_name = "slv_lrclk6", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { .fw_name = "slv_lrclk7", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { .fw_name = "slv_lrclk8", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { .fw_name = "slv_lrclk9", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AUD_TDM_SCLK_MUX(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define AUD_TDM_SCLK_POST_EN(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define AUD_TDM_SCLK(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) aud_tdm##_name##_sclk_post_en, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define AUD_TDM_SCLK_WS(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) aud_tdm##_name##_sclk_post_en, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define AUD_TDM_LRLCK(_name, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Pad master clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { .name = "aud_mst_a_mclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { .name = "aud_mst_b_mclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { .name = "aud_mst_c_mclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { .name = "aud_mst_d_mclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { .name = "aud_mst_e_mclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { .name = "aud_mst_f_mclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Pad bit clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { .name = "aud_mst_a_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { .name = "aud_mst_b_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { .name = "aud_mst_c_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { .name = "aud_mst_d_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { .name = "aud_mst_e_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { .name = "aud_mst_f_sclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Pad sample clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { .name = "aud_mst_a_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { .name = "aud_mst_b_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { .name = "aud_mst_c_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { .name = "aud_mst_d_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { .name = "aud_mst_e_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { .name = "aud_mst_f_lrclk", .index = -1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) CLK_SET_RATE_NO_REPARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Common Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct clk_regmap ddr_arb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct clk_regmap pdm =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct clk_regmap tdmin_a =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct clk_regmap tdmin_b =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct clk_regmap tdmin_c =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct clk_regmap tdmin_lb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct clk_regmap tdmout_a =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static struct clk_regmap tdmout_b =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct clk_regmap tdmout_c =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct clk_regmap frddr_a =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct clk_regmap frddr_b =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static struct clk_regmap frddr_c =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct clk_regmap toddr_a =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct clk_regmap toddr_b =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct clk_regmap toddr_c =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct clk_regmap loopback =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct clk_regmap spdifin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct clk_regmap spdifout =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct clk_regmap resample =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct clk_regmap power_detect =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct clk_regmap spdifout_clk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct clk_regmap pdm_dclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct clk_regmap spdifin_clk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct clk_regmap pdm_sysclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct clk_regmap spdifout_b_clk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct clk_regmap spdifout_clk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct clk_regmap pdm_dclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct clk_regmap spdifin_clk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static struct clk_regmap pdm_sysclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct clk_regmap spdifout_b_clk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct clk_regmap spdifout_clk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct clk_regmap spdifin_clk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct clk_regmap pdm_dclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct clk_regmap pdm_sysclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct clk_regmap spdifout_b_clk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct clk_regmap mst_a_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct clk_regmap mst_b_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static struct clk_regmap mst_c_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static struct clk_regmap mst_d_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static struct clk_regmap mst_e_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct clk_regmap mst_f_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct clk_regmap mst_a_sclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static struct clk_regmap mst_b_sclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct clk_regmap mst_c_sclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct clk_regmap mst_d_sclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct clk_regmap mst_e_sclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static struct clk_regmap mst_f_sclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static struct clk_regmap mst_a_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct clk_regmap mst_b_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct clk_regmap mst_c_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static struct clk_regmap mst_d_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct clk_regmap mst_e_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct clk_regmap mst_f_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static struct clk_regmap mst_a_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct clk_regmap mst_b_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static struct clk_regmap mst_c_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct clk_regmap mst_d_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static struct clk_regmap mst_e_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct clk_regmap mst_f_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct clk_regmap mst_a_lrclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static struct clk_regmap mst_b_lrclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct clk_regmap mst_c_lrclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct clk_regmap mst_d_lrclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static struct clk_regmap mst_e_lrclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static struct clk_regmap mst_f_lrclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct clk_regmap mst_a_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct clk_regmap mst_b_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static struct clk_regmap mst_c_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct clk_regmap mst_d_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct clk_regmap mst_e_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static struct clk_regmap mst_f_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static struct clk_regmap tdmin_a_sclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct clk_regmap tdmin_b_sclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static struct clk_regmap tdmin_c_sclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct clk_regmap tdmin_lb_sclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct clk_regmap tdmout_a_sclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static struct clk_regmap tdmout_b_sclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static struct clk_regmap tdmout_c_sclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct clk_regmap tdmin_a_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static struct clk_regmap tdmin_b_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static struct clk_regmap tdmin_c_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static struct clk_regmap tdmin_lb_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct clk_regmap tdmout_a_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static struct clk_regmap tdmout_b_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static struct clk_regmap tdmout_c_sclk_pre_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct clk_regmap tdmin_a_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static struct clk_regmap tdmin_b_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct clk_regmap tdmin_c_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static struct clk_regmap tdmin_lb_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct clk_regmap tdmout_a_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct clk_regmap tdmout_b_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static struct clk_regmap tdmout_c_sclk_post_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static struct clk_regmap tdmin_a_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static struct clk_regmap tdmin_b_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static struct clk_regmap tdmin_c_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static struct clk_regmap tdmin_lb_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct clk_regmap tdmin_a_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static struct clk_regmap tdmin_b_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static struct clk_regmap tdmin_c_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static struct clk_regmap tdmin_lb_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static struct clk_regmap tdmout_a_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static struct clk_regmap tdmout_b_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct clk_regmap tdmout_c_lrclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* AXG Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct clk_regmap axg_tdmout_a_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static struct clk_regmap axg_tdmout_b_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static struct clk_regmap axg_tdmout_c_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* AXG/G12A Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static struct clk_hw axg_aud_top = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Provide aud_top signal name on axg and g12a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .name = "aud_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .ops = &(const struct clk_ops) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .fw_name = "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static struct clk_regmap mst_a_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static struct clk_regmap mst_b_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static struct clk_regmap mst_c_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static struct clk_regmap mst_d_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static struct clk_regmap mst_e_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static struct clk_regmap mst_f_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static struct clk_regmap mst_a_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static struct clk_regmap mst_b_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static struct clk_regmap mst_c_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static struct clk_regmap mst_d_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct clk_regmap mst_e_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct clk_regmap mst_f_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static struct clk_regmap mst_a_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct clk_regmap mst_b_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static struct clk_regmap mst_c_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct clk_regmap mst_d_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct clk_regmap mst_e_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct clk_regmap mst_f_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* G12a clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static struct clk_regmap g12a_tdmout_a_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) AUD_TDM_SCLK_WS(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static struct clk_regmap g12a_tdmout_b_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) AUD_TDM_SCLK_WS(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static struct clk_regmap g12a_tdmout_c_sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static struct clk_regmap toram =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct clk_regmap spdifout_b =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static struct clk_regmap eqdrc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* SM1 Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static struct clk_regmap sm1_clk81_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .offset = AUDIO_CLK81_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .bit_idx = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .name = "aud_clk81_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .fw_name = "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct clk_regmap sm1_sysclk_a_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .offset = AUDIO_CLK81_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .name = "aud_sysclk_a_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) &sm1_clk81_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static struct clk_regmap sm1_sysclk_a_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .offset = AUDIO_CLK81_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .name = "aud_sysclk_a_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) &sm1_sysclk_a_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static struct clk_regmap sm1_sysclk_b_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .data = &(struct clk_regmap_div_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .offset = AUDIO_CLK81_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .name = "aud_sysclk_b_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) &sm1_clk81_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct clk_regmap sm1_sysclk_b_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .offset = AUDIO_CLK81_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .name = "aud_sysclk_b_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) &sm1_sysclk_b_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static const struct clk_hw *sm1_aud_top_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) &sm1_sysclk_a_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) &sm1_sysclk_b_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static struct clk_regmap sm1_aud_top = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .data = &(struct clk_regmap_mux_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .offset = AUDIO_CLK81_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .name = "aud_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .parent_hws = sm1_aud_top_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .num_parents = ARRAY_SIZE(sm1_aud_top_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .flags = CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static struct clk_regmap resample_b =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static struct clk_regmap tovad =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static struct clk_regmap locker =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static struct clk_regmap spdifin_lb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static struct clk_regmap frddr_d =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static struct clk_regmap toddr_d =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct clk_regmap loopback_b =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static struct clk_regmap sm1_mst_a_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static struct clk_regmap sm1_mst_b_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static struct clk_regmap sm1_mst_c_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static struct clk_regmap sm1_mst_d_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static struct clk_regmap sm1_mst_e_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static struct clk_regmap sm1_mst_f_mclk_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static struct clk_regmap sm1_mst_a_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static struct clk_regmap sm1_mst_b_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static struct clk_regmap sm1_mst_c_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static struct clk_regmap sm1_mst_d_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static struct clk_regmap sm1_mst_e_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static struct clk_regmap sm1_mst_f_mclk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static struct clk_regmap sm1_mst_a_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct clk_regmap sm1_mst_b_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static struct clk_regmap sm1_mst_c_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static struct clk_regmap sm1_mst_d_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static struct clk_regmap sm1_mst_e_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static struct clk_regmap sm1_mst_f_mclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * Array of all clocks provided by this provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * The input clocks of the controller will be populated at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) [AUD_CLKID_PDM] = &pdm.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) [AUD_CLKID_TODDR_A] = &toddr_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) [AUD_CLKID_TODDR_B] = &toddr_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) [AUD_CLKID_TODDR_C] = &toddr_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) [AUD_CLKID_LOOPBACK] = &loopback.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) [AUD_CLKID_SPDIFIN] = &spdifin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) [AUD_CLKID_RESAMPLE] = &resample.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) [AUD_CLKID_TOP] = &axg_aud_top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) [NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * Array of all G12A clocks provided by this provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * The input clocks of the controller will be populated at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) [AUD_CLKID_PDM] = &pdm.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) [AUD_CLKID_TODDR_A] = &toddr_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) [AUD_CLKID_TODDR_B] = &toddr_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) [AUD_CLKID_TODDR_C] = &toddr_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) [AUD_CLKID_LOOPBACK] = &loopback.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) [AUD_CLKID_SPDIFIN] = &spdifin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) [AUD_CLKID_RESAMPLE] = &resample.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) [AUD_CLKID_TOP] = &axg_aud_top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) [NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * Array of all SM1 clocks provided by this provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * The input clocks of the controller will be populated at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) [AUD_CLKID_PDM] = &pdm.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) [AUD_CLKID_TODDR_A] = &toddr_a.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) [AUD_CLKID_TODDR_B] = &toddr_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) [AUD_CLKID_TODDR_C] = &toddr_c.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) [AUD_CLKID_LOOPBACK] = &loopback.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) [AUD_CLKID_SPDIFIN] = &spdifin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) [AUD_CLKID_RESAMPLE] = &resample.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) [AUD_CLKID_TOP] = &sm1_aud_top.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) [AUD_CLKID_TORAM] = &toram.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) [AUD_CLKID_EQDRC] = &eqdrc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) [AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) [AUD_CLKID_TOVAD] = &tovad.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) [AUD_CLKID_LOCKER] = &locker.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) [AUD_CLKID_FRDDR_D] = &frddr_d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) [AUD_CLKID_TODDR_D] = &toddr_d.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) [NR_CLKS] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* Convenience table to populate regmap in .probe(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static struct clk_regmap *const axg_clk_regmaps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) &ddr_arb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) &pdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) &tdmin_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) &tdmin_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) &tdmin_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) &tdmin_lb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) &tdmout_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) &tdmout_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) &tdmout_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) &frddr_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) &frddr_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) &frddr_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) &toddr_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) &toddr_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) &toddr_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) &loopback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) &spdifin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) &spdifout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) &resample,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) &power_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) &mst_a_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) &mst_b_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) &mst_c_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) &mst_d_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) &mst_e_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) &mst_f_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) &mst_a_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) &mst_b_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) &mst_c_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) &mst_d_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) &mst_e_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) &mst_f_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) &mst_a_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) &mst_b_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) &mst_c_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) &mst_d_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) &mst_e_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) &mst_f_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) &spdifout_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) &spdifout_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) &spdifout_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) &spdifin_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) &spdifin_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) &spdifin_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) &pdm_dclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) &pdm_dclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) &pdm_dclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) &pdm_sysclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) &pdm_sysclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) &pdm_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) &mst_a_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) &mst_b_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) &mst_c_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) &mst_d_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) &mst_e_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) &mst_f_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) &mst_a_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) &mst_b_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) &mst_c_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) &mst_d_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) &mst_e_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) &mst_f_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) &mst_a_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) &mst_b_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) &mst_c_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) &mst_d_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) &mst_e_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) &mst_f_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) &mst_a_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) &mst_b_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) &mst_c_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) &mst_d_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) &mst_e_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) &mst_f_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) &mst_a_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) &mst_b_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) &mst_c_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) &mst_d_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) &mst_e_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) &mst_f_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) &mst_a_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) &mst_b_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &mst_c_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) &mst_d_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) &mst_e_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) &mst_f_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) &tdmin_a_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) &tdmin_b_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) &tdmin_c_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) &tdmin_lb_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) &tdmout_a_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) &tdmout_b_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) &tdmout_c_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) &tdmin_a_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) &tdmin_b_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) &tdmin_c_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) &tdmin_lb_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) &tdmout_a_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) &tdmout_b_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) &tdmout_c_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) &tdmin_a_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) &tdmin_b_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) &tdmin_c_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) &tdmin_lb_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) &tdmout_a_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) &tdmout_b_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) &tdmout_c_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) &tdmin_a_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) &tdmin_b_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) &tdmin_c_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) &tdmin_lb_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) &axg_tdmout_a_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) &axg_tdmout_b_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) &axg_tdmout_c_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) &tdmin_a_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) &tdmin_b_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) &tdmin_c_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) &tdmin_lb_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) &tdmout_a_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) &tdmout_b_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) &tdmout_c_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static struct clk_regmap *const g12a_clk_regmaps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) &ddr_arb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) &pdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) &tdmin_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) &tdmin_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) &tdmin_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) &tdmin_lb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) &tdmout_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) &tdmout_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) &tdmout_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) &frddr_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) &frddr_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) &frddr_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) &toddr_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) &toddr_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) &toddr_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) &loopback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) &spdifin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) &spdifout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) &resample,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) &power_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) &spdifout_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) &mst_a_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) &mst_b_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) &mst_c_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) &mst_d_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) &mst_e_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) &mst_f_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) &mst_a_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) &mst_b_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) &mst_c_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) &mst_d_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) &mst_e_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) &mst_f_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) &mst_a_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) &mst_b_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) &mst_c_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) &mst_d_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) &mst_e_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) &mst_f_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) &spdifout_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) &spdifout_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) &spdifout_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) &spdifin_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) &spdifin_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) &spdifin_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) &pdm_dclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) &pdm_dclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) &pdm_dclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) &pdm_sysclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) &pdm_sysclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) &pdm_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) &mst_a_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) &mst_b_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) &mst_c_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) &mst_d_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) &mst_e_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) &mst_f_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) &mst_a_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) &mst_b_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) &mst_c_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) &mst_d_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) &mst_e_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) &mst_f_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) &mst_a_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) &mst_b_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) &mst_c_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) &mst_d_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) &mst_e_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) &mst_f_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) &mst_a_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) &mst_b_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) &mst_c_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) &mst_d_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) &mst_e_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) &mst_f_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) &mst_a_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) &mst_b_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) &mst_c_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) &mst_d_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) &mst_e_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) &mst_f_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) &mst_a_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) &mst_b_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) &mst_c_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) &mst_d_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) &mst_e_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) &mst_f_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) &tdmin_a_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) &tdmin_b_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) &tdmin_c_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) &tdmin_lb_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) &tdmout_a_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) &tdmout_b_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) &tdmout_c_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) &tdmin_a_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) &tdmin_b_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) &tdmin_c_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) &tdmin_lb_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) &tdmout_a_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) &tdmout_b_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) &tdmout_c_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) &tdmin_a_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) &tdmin_b_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) &tdmin_c_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) &tdmin_lb_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) &tdmout_a_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) &tdmout_b_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) &tdmout_c_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) &tdmin_a_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) &tdmin_b_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) &tdmin_c_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) &tdmin_lb_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) &g12a_tdmout_a_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) &g12a_tdmout_b_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) &g12a_tdmout_c_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) &tdmin_a_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) &tdmin_b_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) &tdmin_c_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) &tdmin_lb_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) &tdmout_a_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) &tdmout_b_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) &tdmout_c_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) &spdifout_b_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) &spdifout_b_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) &spdifout_b_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) &g12a_tdm_mclk_pad_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) &g12a_tdm_mclk_pad_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) &g12a_tdm_lrclk_pad_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) &g12a_tdm_lrclk_pad_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) &g12a_tdm_lrclk_pad_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) &g12a_tdm_sclk_pad_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) &g12a_tdm_sclk_pad_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) &g12a_tdm_sclk_pad_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) &toram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) &eqdrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static struct clk_regmap *const sm1_clk_regmaps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) &ddr_arb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) &pdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) &tdmin_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) &tdmin_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) &tdmin_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) &tdmin_lb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) &tdmout_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) &tdmout_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) &tdmout_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) &frddr_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) &frddr_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) &frddr_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) &toddr_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) &toddr_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) &toddr_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) &loopback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) &spdifin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) &spdifout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) &resample,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) &spdifout_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) &sm1_mst_a_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) &sm1_mst_b_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) &sm1_mst_c_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) &sm1_mst_d_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) &sm1_mst_e_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) &sm1_mst_f_mclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) &sm1_mst_a_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) &sm1_mst_b_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) &sm1_mst_c_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) &sm1_mst_d_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) &sm1_mst_e_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) &sm1_mst_f_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) &sm1_mst_a_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) &sm1_mst_b_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) &sm1_mst_c_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) &sm1_mst_d_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) &sm1_mst_e_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) &sm1_mst_f_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) &spdifout_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) &spdifout_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) &spdifout_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) &spdifin_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) &spdifin_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) &spdifin_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) &pdm_dclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) &pdm_dclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) &pdm_dclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) &pdm_sysclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) &pdm_sysclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) &pdm_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) &mst_a_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) &mst_b_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) &mst_c_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) &mst_d_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) &mst_e_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) &mst_f_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) &mst_a_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) &mst_b_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) &mst_c_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) &mst_d_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) &mst_e_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) &mst_f_sclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) &mst_a_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) &mst_b_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) &mst_c_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) &mst_d_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) &mst_e_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) &mst_f_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) &mst_a_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) &mst_b_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) &mst_c_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) &mst_d_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) &mst_e_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) &mst_f_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) &mst_a_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) &mst_b_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) &mst_c_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) &mst_d_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) &mst_e_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) &mst_f_lrclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) &mst_a_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) &mst_b_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) &mst_c_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) &mst_d_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) &mst_e_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) &mst_f_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) &tdmin_a_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) &tdmin_b_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) &tdmin_c_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) &tdmin_lb_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) &tdmout_a_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) &tdmout_b_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) &tdmout_c_sclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) &tdmin_a_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) &tdmin_b_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) &tdmin_c_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) &tdmin_lb_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) &tdmout_a_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) &tdmout_b_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) &tdmout_c_sclk_pre_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) &tdmin_a_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) &tdmin_b_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) &tdmin_c_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) &tdmin_lb_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) &tdmout_a_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) &tdmout_b_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) &tdmout_c_sclk_post_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) &tdmin_a_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) &tdmin_b_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) &tdmin_c_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) &tdmin_lb_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) &g12a_tdmout_a_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) &g12a_tdmout_b_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) &g12a_tdmout_c_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) &tdmin_a_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) &tdmin_b_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) &tdmin_c_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) &tdmin_lb_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) &tdmout_a_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) &tdmout_b_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) &tdmout_c_lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) &spdifout_b_clk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) &spdifout_b_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) &spdifout_b_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) &sm1_tdm_mclk_pad_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) &sm1_tdm_mclk_pad_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) &sm1_tdm_lrclk_pad_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) &sm1_tdm_lrclk_pad_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) &sm1_tdm_lrclk_pad_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) &sm1_tdm_sclk_pad_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) &sm1_tdm_sclk_pad_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) &sm1_tdm_sclk_pad_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) &sm1_aud_top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) &toram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) &eqdrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) &resample_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) &tovad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) &locker,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) &spdifin_lb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) &frddr_d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) &toddr_d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) &loopback_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) &sm1_clk81_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) &sm1_sysclk_a_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) &sm1_sysclk_a_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) &sm1_sysclk_b_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) &sm1_sysclk_b_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static int devm_clk_get_enable(struct device *dev, char *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) clk = devm_clk_get(dev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) dev_err(dev, "failed to get %s", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) dev_err(dev, "failed to enable %s", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ret = devm_add_action_or_reset(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) (void(*)(void *))clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) dev_err(dev, "failed to add reset action on %s", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) struct axg_audio_reset_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) struct reset_controller_dev rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) unsigned long id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) unsigned int *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) unsigned int *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) unsigned int stride = regmap_get_reg_stride(rst->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) *reg = (id / (stride * BITS_PER_BYTE)) * stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) *reg += rst->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) *bit = id % (stride * BITS_PER_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) struct axg_audio_reset_data *rst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) container_of(rcdev, struct axg_audio_reset_data, rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) unsigned int offset, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) regmap_update_bits(rst->map, offset, BIT(bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) assert ? BIT(bit) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) struct axg_audio_reset_data *rst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) container_of(rcdev, struct axg_audio_reset_data, rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) unsigned int val, offset, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) regmap_read(rst->map, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return !!(val & BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) return axg_audio_reset_update(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return axg_audio_reset_update(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ret = axg_audio_reset_assert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return axg_audio_reset_deassert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static const struct reset_control_ops axg_audio_rstc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .assert = axg_audio_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .deassert = axg_audio_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .reset = axg_audio_reset_toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .status = axg_audio_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static const struct regmap_config axg_audio_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .max_register = AUDIO_CLK_SPDIFOUT_B_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct audioclk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct clk_regmap *const *regmap_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) unsigned int regmap_clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) struct clk_hw_onecell_data *hw_onecell_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) unsigned int reset_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) unsigned int reset_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static int axg_audio_clkc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) const struct audioclk_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) struct axg_audio_reset_data *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* Get the mandatory peripheral clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) ret = devm_clk_get_enable(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ret = device_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) dev_err(dev, "failed to reset device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) /* Populate regmap for the regmap backed clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) for (i = 0; i < data->regmap_clk_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) data->regmap_clks[i]->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /* Take care to skip the registered input clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) hw = data->hw_onecell_data->hws[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* array might be sparse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) name = hw->init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) ret = devm_clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) dev_err(dev, "failed to register clock %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) data->hw_onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /* Stop here if there is no reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (!data->reset_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (!rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) rst->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) rst->offset = data->reset_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) rst->rstc.nr_resets = data->reset_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) rst->rstc.ops = &axg_audio_rstc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) rst->rstc.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) rst->rstc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) return devm_reset_controller_register(dev, &rst->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static const struct audioclk_data axg_audioclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .regmap_clks = axg_clk_regmaps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .hw_onecell_data = &axg_audio_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static const struct audioclk_data g12a_audioclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .regmap_clks = g12a_clk_regmaps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .hw_onecell_data = &g12a_audio_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .reset_offset = AUDIO_SW_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .reset_num = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static const struct audioclk_data sm1_audioclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .regmap_clks = sm1_clk_regmaps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .hw_onecell_data = &sm1_audio_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .reset_offset = AUDIO_SM1_SW_RESET0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .reset_num = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static const struct of_device_id clkc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .compatible = "amlogic,axg-audio-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .data = &axg_audioclk_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .compatible = "amlogic,g12a-audio-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .data = &g12a_audioclk_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .compatible = "amlogic,sm1-audio-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .data = &sm1_audioclk_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }, {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) MODULE_DEVICE_TABLE(of, clkc_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) static struct platform_driver axg_audio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .probe = axg_audio_clkc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .name = "axg-audio-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .of_match_table = clkc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) module_platform_driver(axg_audio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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