Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Amlogic Meson-AXG Clock Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016 Baylibre SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Michael Turquette <mturquette@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (c) 2018 Amlogic, inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "meson-aoclk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "axg-aoclk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "clk-dualdiv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * AO Configuration Clock registers offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * Register offsets from the data sheet must be multiplied by 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AO_RTI_PWR_CNTL_REG1	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AO_RTI_PWR_CNTL_REG0	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AO_RTI_GEN_CNTL_REG0	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AO_OSCIN_CNTL		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AO_CRT_CLK_CNTL1	0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AO_SAR_CLK		0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AO_RTC_ALT_CLK_CNTL0	0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AO_RTC_ALT_CLK_CNTL1	0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AXG_AO_GATE(_name, _bit)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static struct clk_regmap axg_aoclk_##_name = {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.data = &(struct clk_regmap_gate_data) {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.offset = (AO_RTI_GEN_CNTL_REG0),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.bit_idx = (_bit),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	},								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.hw.init = &(struct clk_init_data) {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.name =  "axg_ao_" #_name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.ops = &clk_regmap_gate_ops,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.parent_data = &(const struct clk_parent_data) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			.fw_name = "mpeg-clk",				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.num_parents = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.flags = CLK_IGNORE_UNUSED,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	},								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) AXG_AO_GATE(remote, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) AXG_AO_GATE(i2c_master, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) AXG_AO_GATE(i2c_slave, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) AXG_AO_GATE(uart1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) AXG_AO_GATE(uart2, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) AXG_AO_GATE(ir_blaster, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) AXG_AO_GATE(saradc, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static struct clk_regmap axg_aoclk_cts_oscin = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.offset = AO_RTI_PWR_CNTL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.bit_idx = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.name = "cts_oscin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.ops = &clk_regmap_gate_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			.fw_name = "xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static struct clk_regmap axg_aoclk_32k_pre = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.offset = AO_RTC_ALT_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.bit_idx = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.name = "axg_ao_32k_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			&axg_aoclk_cts_oscin.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static const struct meson_clk_dualdiv_param axg_32k_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.dual	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.n1	= 733,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.m1	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.n2	= 732,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.m2	= 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}, {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct clk_regmap axg_aoclk_32k_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.data = &(struct meson_clk_dualdiv_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.n1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			.reg_off = AO_RTC_ALT_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			.shift   = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			.width   = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.n2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			.reg_off = AO_RTC_ALT_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			.shift   = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			.width   = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.m1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			.reg_off = AO_RTC_ALT_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			.shift   = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			.width   = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.m2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			.reg_off = AO_RTC_ALT_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			.shift   = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			.width   = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.dual = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			.reg_off = AO_RTC_ALT_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			.shift   = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			.width   = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.table = axg_32k_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.name = "axg_ao_32k_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.ops = &meson_clk_dualdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			&axg_aoclk_32k_pre.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct clk_regmap axg_aoclk_32k_sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.data = &(struct clk_regmap_mux_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.offset = AO_RTC_ALT_CLK_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.name = "axg_ao_32k_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			&axg_aoclk_32k_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			&axg_aoclk_32k_pre.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct clk_regmap axg_aoclk_32k = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.data = &(struct clk_regmap_gate_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.offset = AO_RTC_ALT_CLK_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.bit_idx = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.name = "axg_ao_32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			&axg_aoclk_32k_sel.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.data = &(struct clk_regmap_mux_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.offset = AO_RTI_PWR_CNTL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.name = "axg_ao_cts_rtc_oscin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			{ .hw = &axg_aoclk_32k.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			{ .fw_name = "ext_32k-0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct clk_regmap axg_aoclk_clk81 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.data = &(struct clk_regmap_mux_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.offset = AO_RTI_PWR_CNTL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.flags = CLK_MUX_ROUND_CLOSEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.name = "axg_ao_clk81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.ops = &clk_regmap_mux_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			{ .fw_name = "mpeg-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			{ .hw = &axg_aoclk_cts_rtc_oscin.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct clk_regmap axg_aoclk_saradc_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.data = &(struct clk_regmap_mux_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.offset = AO_SAR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.name = "axg_ao_saradc_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.ops = &clk_regmap_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.parent_data = (const struct clk_parent_data []) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			{ .fw_name = "xtal", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			{ .hw = &axg_aoclk_clk81.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct clk_regmap axg_aoclk_saradc_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.data = &(struct clk_regmap_div_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.offset = AO_SAR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.name = "axg_ao_saradc_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.ops = &clk_regmap_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			&axg_aoclk_saradc_mux.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct clk_regmap axg_aoclk_saradc_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.data = &(struct clk_regmap_gate_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.offset = AO_SAR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.bit_idx = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.name = "axg_ao_saradc_gate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.ops = &clk_regmap_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.parent_hws = (const struct clk_hw *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			&axg_aoclk_saradc_div.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const unsigned int axg_aoclk_reset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	[RESET_AO_REMOTE]	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	[RESET_AO_I2C_MASTER]	= 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	[RESET_AO_I2C_SLAVE]	= 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	[RESET_AO_UART1]	= 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	[RESET_AO_UART2]	= 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	[RESET_AO_IR_BLASTER]	= 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct clk_regmap *axg_aoclk_regmap[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	&axg_aoclk_remote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	&axg_aoclk_i2c_master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	&axg_aoclk_i2c_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	&axg_aoclk_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	&axg_aoclk_uart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	&axg_aoclk_ir_blaster,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	&axg_aoclk_saradc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	&axg_aoclk_cts_oscin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	&axg_aoclk_32k_pre,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	&axg_aoclk_32k_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	&axg_aoclk_32k_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	&axg_aoclk_32k,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	&axg_aoclk_cts_rtc_oscin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	&axg_aoclk_clk81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	&axg_aoclk_saradc_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	&axg_aoclk_saradc_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	&axg_aoclk_saradc_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		[CLKID_AO_REMOTE]	= &axg_aoclk_remote.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		[CLKID_AO_I2C_MASTER]	= &axg_aoclk_i2c_master.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		[CLKID_AO_I2C_SLAVE]	= &axg_aoclk_i2c_slave.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		[CLKID_AO_UART1]	= &axg_aoclk_uart1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		[CLKID_AO_UART2]	= &axg_aoclk_uart2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		[CLKID_AO_IR_BLASTER]	= &axg_aoclk_ir_blaster.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		[CLKID_AO_SAR_ADC]	= &axg_aoclk_saradc.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		[CLKID_AO_CLK81]	= &axg_aoclk_clk81.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		[CLKID_AO_SAR_ADC_SEL]	= &axg_aoclk_saradc_mux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		[CLKID_AO_SAR_ADC_DIV]	= &axg_aoclk_saradc_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		[CLKID_AO_SAR_ADC_CLK]	= &axg_aoclk_saradc_gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		[CLKID_AO_CTS_OSCIN]	= &axg_aoclk_cts_oscin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		[CLKID_AO_32K_PRE]	= &axg_aoclk_32k_pre.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		[CLKID_AO_32K_DIV]	= &axg_aoclk_32k_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		[CLKID_AO_32K_SEL]	= &axg_aoclk_32k_sel.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		[CLKID_AO_32K]		= &axg_aoclk_32k.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.num = NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct meson_aoclk_data axg_aoclkc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.reset		= axg_aoclk_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.clks		= axg_aoclk_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.hw_data	= &axg_aoclk_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct of_device_id axg_aoclkc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.compatible	= "amlogic,meson-axg-aoclkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.data		= &axg_aoclkc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_DEVICE_TABLE(of, axg_aoclkc_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct platform_driver axg_aoclkc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.probe		= meson_aoclkc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.name	= "axg-aoclkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.of_match_table = axg_aoclkc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) module_platform_driver(axg_aoclkc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_LICENSE("GPL v2");