^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) # Amlogic clock drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) # Amlogic Clock controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o