^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct mtk_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) int regofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int reg = data->regofs + ((id / 32) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return regmap_write(data->regmap, reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return regmap_write(data->regmap, reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int mtk_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) BIT(id % 32), ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) BIT(id % 32), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int mtk_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = mtk_reset_assert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return mtk_reset_deassert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ret = mtk_reset_assert_set_clr(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return mtk_reset_deassert_set_clr(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct reset_control_ops mtk_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .assert = mtk_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .deassert = mtk_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .reset = mtk_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct reset_control_ops mtk_reset_ops_set_clr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .assert = mtk_reset_assert_set_clr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .deassert = mtk_reset_deassert_set_clr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .reset = mtk_reset_set_clr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void mtk_register_reset_controller_common(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int num_regs, int regofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const struct reset_control_ops *reset_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct mtk_reset *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) regmap = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pr_err("Cannot find regmap for %pOF: %ld\n", np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PTR_ERR(regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) data->regofs = regofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) data->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) data->rcdev.nr_resets = num_regs * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) data->rcdev.ops = reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) data->rcdev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = reset_controller_register(&data->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pr_err("could not register reset controller: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void mtk_register_reset_controller(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int num_regs, int regofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mtk_register_reset_controller_common(np, num_regs, regofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) &mtk_reset_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void mtk_register_reset_controller_set_clr(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int num_regs, int regofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mtk_register_reset_controller_common(np, num_regs, regofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) &mtk_reset_ops_set_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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