^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Owen Chen <owen.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __DRV_CLK_MTK_MUX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __DRV_CLK_MTK_MUX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct mtk_clk_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) const struct mtk_mux *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct mtk_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 mux_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 set_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 clr_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 upd_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 mux_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 gate_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) s8 upd_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) signed char num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern const struct clk_ops mtk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern const struct clk_ops mtk_mux_clr_set_upd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern const struct clk_ops mtk_mux_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) _gate, _upd_ofs, _upd, _flags, _ops) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .mux_ofs = _mux_ofs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .set_ofs = _mux_set_ofs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .clr_ofs = _mux_clr_ofs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .upd_ofs = _upd_ofs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .mux_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .mux_width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .gate_shift = _gate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .upd_shift = _upd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .parent_names = _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .num_parents = ARRAY_SIZE(_parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .ops = &_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) _gate, _upd_ofs, _upd, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) _gate, _upd_ofs, _upd, _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mtk_mux_gate_clr_set_upd_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) _gate, _upd_ofs, _upd) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) _width, _gate, _upd_ofs, _upd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int mtk_clk_register_muxes(const struct mtk_mux *muxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int num, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk_onecell_data *clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif /* __DRV_CLK_MTK_MUX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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