^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Owen Chen <owen.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) return container_of(hw, struct mtk_clk_mux, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int mtk_clk_mux_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 mask = BIT(mux->data->gate_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return regmap_update_bits(mux->regmap, mux->data->mux_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) mask, ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void mtk_clk_mux_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 mask = BIT(mux->data->gate_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return regmap_write(mux->regmap, mux->data->clr_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) BIT(mux->data->gate_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) regmap_write(mux->regmap, mux->data->set_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) BIT(mux->data->gate_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) regmap_read(mux->regmap, mux->data->mux_ofs, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return (val & BIT(mux->data->gate_shift)) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 mask = GENMASK(mux->data->mux_width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) regmap_read(mux->regmap, mux->data->mux_ofs, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) val = (val >> mux->data->mux_shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 mask = GENMASK(mux->data->mux_width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spin_lock_irqsave(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __acquire(mux->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) index << mux->data->mux_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) spin_unlock_irqrestore(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __release(mux->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 mask = GENMASK(mux->data->mux_width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 val, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) spin_lock_irqsave(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __acquire(mux->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val = (orig & ~(mask << mux->data->mux_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) | (index << mux->data->mux_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (val != orig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regmap_write(mux->regmap, mux->data->clr_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mask << mux->data->mux_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) regmap_write(mux->regmap, mux->data->set_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) index << mux->data->mux_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (mux->data->upd_shift >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) regmap_write(mux->regmap, mux->data->upd_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) BIT(mux->data->upd_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) spin_unlock_irqrestore(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __release(mux->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const struct clk_ops mtk_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .get_parent = mtk_clk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .set_parent = mtk_clk_mux_set_parent_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct clk_ops mtk_mux_clr_set_upd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .get_parent = mtk_clk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .set_parent = mtk_clk_mux_set_parent_setclr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const struct clk_ops mtk_mux_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .enable = mtk_clk_mux_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .disable = mtk_clk_mux_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .is_enabled = mtk_clk_mux_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .get_parent = mtk_clk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .set_parent = mtk_clk_mux_set_parent_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .enable = mtk_clk_mux_enable_setclr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .disable = mtk_clk_mux_disable_setclr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .is_enabled = mtk_clk_mux_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .get_parent = mtk_clk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .set_parent = mtk_clk_mux_set_parent_setclr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mtk_clk_mux *clk_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!clk_mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) init.name = mux->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) init.flags = mux->flags | CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) init.parent_names = mux->parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) init.num_parents = mux->num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) init.ops = mux->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clk_mux->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clk_mux->data = mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk_mux->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clk_mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clk = clk_register(NULL, &clk_mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) kfree(clk_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int mtk_clk_register_muxes(const struct mtk_mux *muxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int num, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct clk_onecell_data *clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) regmap = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pr_err("Cannot find regmap for %pOF: %ld\n", node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PTR_ERR(regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const struct mtk_mux *mux = &muxes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk = mtk_clk_register_mux(mux, regmap, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pr_err("Failed to register clk %s: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mux->name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk_data->clks[mux->id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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