^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (!clk_data->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) clk_data->clk_num = clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) for (i = 0; i < clk_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) clk_data->clks[i] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int num, struct clk_onecell_data *clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const struct mtk_fixed_clk *rc = &clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[rc->id]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clk = clk_register_fixed_rate(NULL, rc->name, rc->parent, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) rc->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pr_err("Failed to register clk %s: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) rc->name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) clk_data->clks[rc->id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int num, struct clk_onecell_data *clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct mtk_fixed_factor *ff = &clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[ff->id]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) CLK_SET_RATE_PARENT, ff->mult, ff->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pr_err("Failed to register clk %s: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ff->name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clk_data->clks[ff->id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int mtk_clk_register_gates_with_dev(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const struct mtk_gate *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int num, struct clk_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regmap = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pr_err("Cannot find regmap for %pOF: %ld\n", node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PTR_ERR(regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const struct mtk_gate *gate = &clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!IS_ERR_OR_NULL(clk_data->clks[gate->id]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk = mtk_clk_register_gate(gate->name, gate->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) gate->regs->set_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) gate->regs->clr_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) gate->regs->sta_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) gate->shift, gate->ops, gate->flags, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pr_err("Failed to register clk %s: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) gate->name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_data->clks[gate->id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int mtk_clk_register_gates(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const struct mtk_gate *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int num, struct clk_onecell_data *clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return mtk_clk_register_gates_with_dev(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clks, num, clk_data, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void __iomem *base, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct clk_mux *mux = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct clk_gate *gate = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct clk_divider *div = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (mc->mux_shift >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mux->reg = base + mc->mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mux->mask = BIT(mc->mux_width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mux->shift = mc->mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mux->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mux->flags = mc->mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mux_hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mux_ops = &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) parent_names = mc->parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) num_parents = mc->num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) parent = mc->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) parent_names = &parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (mc->gate_shift >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) gate->reg = base + mc->gate_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) gate->bit_idx = mc->gate_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) gate->flags = CLK_GATE_SET_TO_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) gate->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) gate_hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) gate_ops = &clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (mc->divider_shift >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) div = kzalloc(sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) div->reg = base + mc->divider_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) div->shift = mc->divider_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) div->width = mc->divider_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) div->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) div_hw = &div->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) div_ops = &clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) clk = clk_register_composite(NULL, mc->name, parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mux_hw, mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) div_hw, div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) gate_hw, gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) kfree(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) void mtk_clk_register_composites(const struct mtk_composite *mcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int num, void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct clk_onecell_data *clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) const struct mtk_composite *mc = &mcs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mc->id]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) clk = mtk_clk_register_composite(mc, base, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_err("Failed to register clk %s: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mc->name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) clk_data->clks[mc->id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int num, void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct clk_onecell_data *clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) const struct mtk_clk_divider *mcd = &mcds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mcd->id]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clk = clk_register_divider(NULL, mcd->name, mcd->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mcd->flags, base + mcd->div_reg, mcd->div_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mcd->div_width, mcd->clk_divider_flags, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pr_err("Failed to register clk %s: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mcd->name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) clk_data->clks[mcd->id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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