^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Fabien Parent <fparent@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/mt8516-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static DEFINE_SPINLOCK(mt8516_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct mtk_fixed_clk fixed_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const struct mtk_fixed_factor top_divs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const char * const uart0_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "univpll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const char * const ahb_infra_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "mainpll_d11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "mainpll_d10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const char * const msdc0_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "univpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "mainpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "univpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "mainpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "mmpll_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "mmpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const char * const uart1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "univpll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const char * const msdc1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "univpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "mainpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "univpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "mainpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "mmpll_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "mmpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const char * const pmicspi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "univpll_d20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "usb_phy48m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "univpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "clk26m_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const char * const qaxi_aud26m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "ahb_infra_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const char * const aud_intbus_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "mainpll_d22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "mainpll_d11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const char * const nfi2x_pad_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "mainpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "mainpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "mainpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "mainpll_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "mainpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "mainpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const char * const nfi1x_pad_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "ahb_infra_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "nfi1x_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const char * const usb_78m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "univpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "mainpll_d20"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const char * const spinor_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "clk26m_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "mainpll_d40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "univpll_d24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "univpll_d20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "mainpll_d20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "mainpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "univpll_d12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const char * const msdc2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "univpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "mainpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "univpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "mainpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "mmpll_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "mmpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const char * const eth_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "mainpll_d40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "univpll_d24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "univpll_d20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "mainpll_d20"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const char * const aud1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "apll1_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const char * const aud2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "apll2_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const char * const aud_engen1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "rg_apll1_d2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "rg_apll1_d4_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "rg_apll1_d8_en"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const char * const aud_engen2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "rg_apll2_d2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "rg_apll2_d4_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "rg_apll2_d8_en"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const char * const i2c_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "univpll_d20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "univpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "univpll_d12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const char * const aud_i2s0_m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "rg_aud1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "rg_aud2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const char * const pwm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "univpll_d12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const char * const spi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "univpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "univpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "univpll_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const char * const aud_spdifin_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "univpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const char * const uart2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "univpll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const char * const bsi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "mainpll_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "mainpll_d20"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const char * const dbg_atclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "mainpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "univpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const char * const csw_nfiecc_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "mainpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "mainpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "mainpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const char * const nfiecc_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "nfi2x_pad_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "mainpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "csw_nfiecc_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static struct mtk_composite top_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* CLK_MUX_SEL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0x000, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0x000, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0x000, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0x000, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0x000, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0x000, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x000, 26, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0x000, 27, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* CLK_MUX_SEL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x004, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x004, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x004, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* CLK_MUX_SEL8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x040, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0x040, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 0x040, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0x040, 22, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 0x040, 23, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0x040, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x040, 26, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0x040, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* CLK_SEL_9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0x044, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x044, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 0x044, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 0x044, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 0x044, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 0x044, 17, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0x044, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* CLK_MUX_SEL13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0x07c, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0x07c, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0x07c, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 0x07c, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 0x07c, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0x07c, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0x07c, 10, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 0x07c, 13, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const char * const ifr_mux1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "armpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "univpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "mainpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const char * const ifr_eth_25m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "eth_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "rg_eth"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const char * const ifr_i2c0_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "ahb_infra_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "rg_i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct mtk_composite ifr_muxes[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .div_reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .div_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .div_width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct mtk_clk_divider top_adj_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0x0048, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 0x0048, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 0x0048, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 0x0048, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 0x004c, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 0x004c, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 0x004c, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 0x004c, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 0x0078, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct mtk_gate_regs top1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .set_ofs = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .clr_ofs = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .sta_ofs = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const struct mtk_gate_regs top2_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .set_ofs = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .clr_ofs = 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .sta_ofs = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const struct mtk_gate_regs top3_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .set_ofs = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .clr_ofs = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .sta_ofs = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const struct mtk_gate_regs top4_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .set_ofs = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .clr_ofs = 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .sta_ofs = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct mtk_gate_regs top5_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .set_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .clr_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .sta_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define GATE_TOP1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .regs = &top1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define GATE_TOP2(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .regs = &top2_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define GATE_TOP2_I(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .regs = &top2_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define GATE_TOP3(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .regs = &top3_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define GATE_TOP4_I(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .regs = &top4_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define GATE_TOP5(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .regs = &top5_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .ops = &mtk_clk_gate_ops_no_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const struct mtk_gate top_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* TOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* TOP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* TOP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* TOP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* TOP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static void __init mtk_topckgen_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) &mt8516_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) base, &mt8516_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8516-topckgen", mtk_topckgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static void __init mtk_infracfg_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) &mt8516_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8516-infracfg", mtk_infracfg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define MT8516_PLL_FMAX (1502UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define CON0_MT8516_RST_BAR BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) _pcw_shift, _div_table) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .pwr_reg = _pwr_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .en_mask = _en_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .rst_bar_mask = CON0_MT8516_RST_BAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .fmax = MT8516_PLL_FMAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .pcwbits = _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .pd_reg = _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .tuner_reg = _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .pcw_reg = _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .pcw_shift = _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .div_table = _div_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) _pcw_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const struct mtk_pll_div_table mmpll_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) { .div = 0, .freq = MT8516_PLL_FMAX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) { .div = 1, .freq = 1000000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) { .div = 2, .freq = 604500000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) { .div = 3, .freq = 253500000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) { .div = 4, .freq = 126750000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) { } /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const struct mtk_pll_data plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 21, 0x0104, 24, 0, 0x0104, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0x00000001, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0x00000001, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 31, 0x0180, 1, 0x0194, 0x0184, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0x00000001, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static void __init mtk_apmixedsys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8516-apmixedsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mtk_apmixedsys_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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