Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *         Fabien Parent <fparent@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/mt8516-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static const struct mtk_gate_regs aud_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	.set_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.clr_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GATE_AUD(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		.id = _id,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		.name = _name,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		.parent_name = _parent,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		.regs = &aud_cg_regs,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		.shift = _shift,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		.ops = &mtk_clk_gate_ops_no_setclr,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct mtk_gate aud_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void __init mtk_audsys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			__func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8516-audsys", mtk_audsys_init);