Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) // Author: Weiyi Lu <weiyi.lu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/mt8183-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const struct mtk_gate_regs vdec0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	.set_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.clr_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct mtk_gate_regs vdec1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.set_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.clr_ofs = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.sta_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GATE_VDEC0_I(_id, _name, _parent, _shift)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		&mtk_clk_gate_ops_setclr_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GATE_VDEC1_I(_id, _name, _parent, _shift)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		&mtk_clk_gate_ops_setclr_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct mtk_gate vdec_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	/* VDEC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_vdec", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	/* VDEC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int clk_mt8183_vdec_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct of_device_id of_match_clk_mt8183_vdec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	{ .compatible = "mediatek,mt8183-vdecsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct platform_driver clk_mt8183_vdec_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	.probe = clk_mt8183_vdec_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		.name = "clk-mt8183-vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		.of_match_table = of_match_clk_mt8183_vdec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) builtin_platform_driver(clk_mt8183_vdec_drv);