^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Weiyi Lu <weiyi.lu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/mt8183-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const struct mtk_gate_regs ipu_conn_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .set_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .clr_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct mtk_gate_regs ipu_conn_apb_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .set_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .clr_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .sta_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct mtk_gate_regs ipu_conn_axi_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .set_ofs = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .clr_ofs = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .sta_ofs = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct mtk_gate_regs ipu_conn_axi1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .set_ofs = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .clr_ofs = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .sta_ofs = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct mtk_gate_regs ipu_conn_axi2_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .set_ofs = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .clr_ofs = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .sta_ofs = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GATE_IPU_CONN(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) &mtk_clk_gate_ops_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) &mtk_clk_gate_ops_no_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) &mtk_clk_gate_ops_no_setclr_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) &mtk_clk_gate_ops_no_setclr_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) &mtk_clk_gate_ops_no_setclr_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct mtk_gate ipu_conn_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GATE_IPU_CONN(CLK_IPU_CONN_IPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "ipu_conn_ipu", "dsp_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) GATE_IPU_CONN(CLK_IPU_CONN_AHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "ipu_conn_ahb", "dsp_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GATE_IPU_CONN(CLK_IPU_CONN_AXI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "ipu_conn_axi", "dsp_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GATE_IPU_CONN(CLK_IPU_CONN_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "ipu_conn_isp", "dsp_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GATE_IPU_CONN(CLK_IPU_CONN_CAM_ADL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "ipu_conn_cam_adl", "dsp_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GATE_IPU_CONN(CLK_IPU_CONN_IMG_ADL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "ipu_conn_img_adl", "dsp_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GATE_IPU_CONN_APB(CLK_IPU_CONN_DAP_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "ipu_conn_dap_rx", "dsp1_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AXI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "ipu_conn_apb2axi", "dsp1_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "ipu_conn_apb2ahb", "dsp1_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU_CAB1TO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "ipu_conn_ipu_cab1to2", "dsp1_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU1_CAB1TO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "ipu_conn_ipu1_cab1to2", "dsp1_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU2_CAB1TO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "ipu_conn_ipu2_cab1to2", "dsp1_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GATE_IPU_CONN_AXI1_I(CLK_IPU_CONN_CAB3TO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "ipu_conn_cab3to3", "dsp1_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB2TO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "ipu_conn_cab2to1", "dsp1_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB3TO1_SLICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "ipu_conn_cab3to1_slice", "dsp1_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk_data = mtk_alloc_clk_data(CLK_IPU_CONN_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mtk_clk_register_gates(node, ipu_conn_clks, ARRAY_SIZE(ipu_conn_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .compatible = "mediatek,mt8183-ipu_conn", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct platform_driver clk_mt8183_ipu_conn_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .probe = clk_mt8183_ipu_conn_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .name = "clk-mt8183-ipu_conn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .of_match_table = of_match_clk_mt8183_ipu_conn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) builtin_platform_driver(clk_mt8183_ipu_conn_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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