Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) // Author: Weiyi Lu <weiyi.lu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/mt8183-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const struct mtk_gate_regs ipu_core0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	.set_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.clr_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GATE_IPU_CORE0(_id, _name, _parent, _shift)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	GATE_MTK(_id, _name, _parent, &ipu_core0_cg_regs, _shift,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		&mtk_clk_gate_ops_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct mtk_gate ipu_core0_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	GATE_IPU_CORE0(CLK_IPU_CORE0_JTAG, "ipu_core0_jtag", "dsp_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	GATE_IPU_CORE0(CLK_IPU_CORE0_AXI, "ipu_core0_axi", "dsp_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	GATE_IPU_CORE0(CLK_IPU_CORE0_IPU, "ipu_core0_ipu", "dsp_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	clk_data = mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	mtk_clk_register_gates(node, ipu_core0_clks, ARRAY_SIZE(ipu_core0_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	{ .compatible = "mediatek,mt8183-ipu_core0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct platform_driver clk_mt8183_ipu_core0_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	.probe = clk_mt8183_ipu_core0_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		.name = "clk-mt8183-ipu_core0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		.of_match_table = of_match_clk_mt8183_ipu_core0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) builtin_platform_driver(clk_mt8183_ipu_core0_drv);