Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) // Author: Weiyi Lu <weiyi.lu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/mt8183-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const struct mtk_gate_regs img_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	.set_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.clr_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GATE_IMG(_id, _name, _parent, _shift)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		&mtk_clk_gate_ops_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct mtk_gate img_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	GATE_IMG(CLK_IMG_LARB5, "img_larb5", "img_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	GATE_IMG(CLK_IMG_LARB2, "img_larb2", "img_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	GATE_IMG(CLK_IMG_DIP, "img_dip", "img_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "img_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	GATE_IMG(CLK_IMG_DPE, "img_dpe", "img_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	GATE_IMG(CLK_IMG_RSC, "img_rsc", "img_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	GATE_IMG(CLK_IMG_MFB, "img_mfb", "img_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	GATE_IMG(CLK_IMG_WPE_A, "img_wpe_a", "img_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	GATE_IMG(CLK_IMG_WPE_B, "img_wpe_b", "img_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int clk_mt8183_img_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct of_device_id of_match_clk_mt8183_img[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	{ .compatible = "mediatek,mt8183-imgsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct platform_driver clk_mt8183_img_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	.probe = clk_mt8183_img_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		.name = "clk-mt8183-img",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		.of_match_table = of_match_clk_mt8183_img,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) builtin_platform_driver(clk_mt8183_img_drv);