^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Weiyi Lu <weiyi.lu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt8183-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct mtk_gate_regs audio0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .set_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .clr_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct mtk_gate_regs audio1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .set_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .clr_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .sta_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GATE_AUDIO0(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) &mtk_clk_gate_ops_no_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GATE_AUDIO1(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) &mtk_clk_gate_ops_no_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct mtk_gate audio_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* AUDIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_eng1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) GATE_AUDIO0(CLK_AUDIO_24M, "aud_24m", "aud_eng2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) GATE_AUDIO0(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GATE_AUDIO0(CLK_AUDIO_TDM, "aud_tdm", "apll12_divb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* AUDIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GATE_AUDIO1(CLK_AUDIO_I2S1, "aud_i2s1", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GATE_AUDIO1(CLK_AUDIO_I2S2, "aud_i2s2", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GATE_AUDIO1(CLK_AUDIO_I2S3, "aud_i2s3", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GATE_AUDIO1(CLK_AUDIO_I2S4, "aud_i2s4", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GATE_AUDIO1(CLK_AUDIO_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int clk_mt8183_audio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) r = devm_of_platform_populate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) of_clk_del_provider(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct of_device_id of_match_clk_mt8183_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .compatible = "mediatek,mt8183-audiosys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct platform_driver clk_mt8183_audio_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .probe = clk_mt8183_audio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = "clk-mt8183-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .of_match_table = of_match_clk_mt8183_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) builtin_platform_driver(clk_mt8183_audio_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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