^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-cpumux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/mt8173-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * For some clocks, we don't care what their actual rates are. And these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * clocks may change their rate on different products or different scenarios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * So we model these clocks' rate as 0, to denote it's not an actual rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DUMMY_RATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static DEFINE_SPINLOCK(mt8173_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct mtk_fixed_clk fixed_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct mtk_fixed_factor top_divs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const char * const axi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "dmpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "dmpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const char * const mem_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "dmpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const char * const ddrphycfg_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "syspll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const char * const mm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "vencpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "main_h364m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "dmpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const char * const pwm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "univpll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const char * const vdec_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "vcodecpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "tvdpll_445p5m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "vencpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "mmpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "dmpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "dmpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const char * const venc_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "vcodecpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "tvdpll_445p5m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "vencpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "dmpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "dmpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const char * const mfg_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "mmpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "dmpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "univpll2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const char * const camtg_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "univpll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const char * const uart_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const char * const spi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "univpll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const char * const usb20_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "univpll3_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const char * const usb30_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "usb_syspll_125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const char * const msdc50_0_h_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "univpll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const char * const msdc50_0_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "msdcpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "msdcpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "msdcpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "vencpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "tvdpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "mmpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "msdcpll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "msdcpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "msdcpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const char * const msdc30_1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "msdcpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "vencpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const char * const msdc30_2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "msdcpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "vencpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const char * const msdc30_3_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "msdcpll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "msdcpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "msdcpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "msdcpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "vencpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "msdcpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "msdcpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "msdcpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const char * const audio_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "syspll4_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "syspll1_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const char * const aud_intbus_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "dmpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "dmpll_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const char * const pmicspi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "syspll1_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "dmpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "dmpll_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const char * const scp_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "dmpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "dmpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const char * const atb_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "dmpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const char * const venc_lt_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "vcodecpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "tvdpll_445p5m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "vencpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "vcodecpll_370p5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "dmpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const char * const dpi0_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "tvdpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "tvdpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "tvdpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "tvdpll_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const char * const irda_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "syspll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const char * const cci400_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "vencpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "armca7pll_754m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "armca7pll_502m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "syspll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "msdcpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "dmpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const char * const aud_1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "apll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const char * const aud_2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "apll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const char * const mem_mfg_in_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "mmpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) "dmpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "clk26m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const char * const axi_mfg_in_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "axi_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "dmpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const char * const scam_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "dmpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const char * const spinfi_ifr_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "univpll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const char * const hdmi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "hdmitx_dig_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "hdmitxpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "hdmitxpll_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const char * const dpilvds_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "lvdspll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "lvdspll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "lvdspll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "lvdspll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "fpc_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static const char * const msdc50_2_h_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "univpll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const char * const hdcp_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const char * const hdcp_24m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "univpll_d52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const char * const rtc_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "clkrtc_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "clkrtc_ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "univpll3_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const char * const i2s0_m_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "apll1_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "apll2_div1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const char * const i2s1_m_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "apll1_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "apll2_div2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const char * const i2s2_m_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "apll1_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "apll2_div3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const char * const i2s3_m_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "apll1_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "apll2_div4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const char * const i2s3_b_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) "apll1_div5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) "apll2_div5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const char * const ca53_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) "armca7pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "mainpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "univpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const char * const ca72_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "armca15pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "mainpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "univpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct mtk_composite cpu_muxes[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const struct mtk_composite top_muxes[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* CLK_CFG_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* CLK_CFG_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* CLK_CFG_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* CLK_CFG_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* CLK_CFG_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* CLK_CFG_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* CLK_CFG_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * The dpi0_sel clock should not propagate rate changes to its parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * clock so the dpi driver can have full control over PLL and divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* CLK_CFG_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* CLK_CFG_12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* CLK_CFG_13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct mtk_gate_regs infra_cg_regs __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .set_ofs = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .clr_ofs = 0x0044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .sta_ofs = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define GATE_ICG(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .regs = &infra_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const struct mtk_gate infra_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const struct mtk_fixed_factor infra_divs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const struct mtk_gate_regs peri0_cg_regs __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .set_ofs = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .clr_ofs = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .sta_ofs = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static const struct mtk_gate_regs peri1_cg_regs __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .set_ofs = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .clr_ofs = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .sta_ofs = 0x001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define GATE_PERI0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .regs = &peri0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define GATE_PERI1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .regs = &peri1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const struct mtk_gate peri_gates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* PERI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* PERI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static const char * const uart_ck_sel_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "uart_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct mtk_composite peri_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const struct mtk_gate_regs cg_regs_4_8_0 __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .set_ofs = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .clr_ofs = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .sta_ofs = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define GATE_IMG(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .regs = &cg_regs_4_8_0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const struct mtk_gate img_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .set_ofs = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .clr_ofs = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .sta_ofs = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct mtk_gate_regs vdec1_cg_regs __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .set_ofs = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .clr_ofs = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .sta_ofs = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define GATE_VDEC0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .regs = &vdec0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define GATE_VDEC1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .regs = &vdec1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const struct mtk_gate vdec_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define GATE_VENC(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .regs = &cg_regs_4_8_0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const struct mtk_gate venc_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define GATE_VENCLT(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .regs = &cg_regs_4_8_0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const struct mtk_gate venclt_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static struct clk_onecell_data *mt8173_top_clk_data __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static void __init mtk_clk_enable_critical(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static void __init mtk_topckgen_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) &mt8173_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mtk_clk_enable_critical();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static void __init mtk_infrasys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mtk_register_reset_controller(node, 2, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static void __init mtk_pericfg_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) &mt8173_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) mtk_register_reset_controller(node, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct mtk_clk_usb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) u32 reg_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .parent = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .reg_ofs = _reg_ofs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const struct mtk_clk_usb apmixed_usb[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) APMIXED_USB(CLK_APMIXED_REF2USB_TX, "ref2usb_tx", "clk26m", 0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define MT8173_PLL_FMAX (3000UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define CON0_MT8173_RST_BAR BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) _pcw_shift, _div_table) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .pwr_reg = _pwr_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .en_mask = _en_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .rst_bar_mask = CON0_MT8173_RST_BAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .fmax = MT8173_PLL_FMAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .pcwbits = _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .pd_reg = _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .tuner_reg = _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .pcw_reg = _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .pcw_shift = _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .div_table = _div_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) _pcw_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const struct mtk_pll_div_table mmpll_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) { .div = 0, .freq = MT8173_PLL_FMAX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) { .div = 1, .freq = 1000000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) { .div = 2, .freq = 702000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) { .div = 3, .freq = 253500000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) { .div = 4, .freq = 126750000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) { } /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const struct mtk_pll_data plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static void __init mtk_apmixedsys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (!clk_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) for (i = 0; i < ARRAY_SIZE(apmixed_usb); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) const struct mtk_clk_usb *cku = &apmixed_usb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) clk = mtk_clk_register_ref2usb_tx(cku->name, cku->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) base + cku->reg_ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) pr_err("Failed to register clk %s: %ld\n", cku->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) clk_data->clks[cku->id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) mtk_clk_enable_critical();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) mtk_apmixedsys_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static void __init mtk_imgsys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static void __init mtk_vdecsys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static void __init mtk_vencsys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static void __init mtk_vencltsys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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