^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/mt8173-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static const struct mtk_gate_regs mm0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .set_ofs = 0x0104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .clr_ofs = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .sta_ofs = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct mtk_gate_regs mm1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .set_ofs = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .clr_ofs = 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .sta_ofs = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GATE_MM0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .regs = &mm0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GATE_MM1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .regs = &mm1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const struct mtk_gate mt8173_mm_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* MM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* MM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct clk_mt8173_mm_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const struct mtk_gate *gates_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int gates_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct clk_mt8173_mm_driver_data mt8173_mmsys_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .gates_clk = mt8173_mm_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .gates_num = ARRAY_SIZE(mt8173_mm_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int clk_mt8173_mm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct device_node *node = dev->parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const struct clk_mt8173_mm_driver_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) data = &mt8173_mmsys_driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct platform_driver clk_mt8173_mm_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "clk-mt8173-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .probe = clk_mt8173_mm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) builtin_platform_driver(clk_mt8173_mm_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags