^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2020 BayLibre, SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Fabien Parent <fparent@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/mt8167-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static DEFINE_SPINLOCK(mt8167_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct mtk_fixed_clk fixed_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 75000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 52500000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const struct mtk_fixed_factor top_divs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FACTOR(CLK_TOP_MIPI_26M, "mipi_26m", "clk26m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const char * const uart0_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "univpll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const char * const gfmux_emi1x_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "dmpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const char * const emi_ddrphy_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "gfmux_emi1x_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "gfmux_emi1x_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char * const ahb_infra_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "mainpll_d11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "mainpll_d10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char * const csw_mux_mfg_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "mainpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "univpll_d24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "mmpll380m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const char * const msdc0_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "univpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "mainpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "univpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "mainpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "mmpll_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "mmpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const char * const camtg_mm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "usb_phy48m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "univpll_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const char * const pwm_mm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "univpll_d12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const char * const uart1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "univpll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const char * const msdc1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "univpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "mainpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "univpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "mainpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "mmpll_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "mmpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const char * const spm_52m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "univpll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const char * const pmicspi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "univpll_d20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "usb_phy48m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "univpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "clk26m_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const char * const qaxi_aud26m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "ahb_infra_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const char * const aud_intbus_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "mainpll_d22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "mainpll_d11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const char * const nfi2x_pad_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "mainpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "mainpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "mainpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "mainpll_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "mainpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "mainpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const char * const nfi1x_pad_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "ahb_infra_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "nfi1x_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const char * const mfg_mm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "csw_mux_mfg_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "mainpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "mainpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "mainpll_d14"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const char * const ddrphycfg_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "mainpll_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const char * const smi_mm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "univpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "mainpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "mainpll_d14"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const char * const usb_78m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "univpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "mainpll_d20"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const char * const scam_mm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "mainpll_d14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "mainpll_d12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const char * const spinor_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "clk26m_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "mainpll_d40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "univpll_d24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "univpll_d20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "mainpll_d20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "mainpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "univpll_d12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const char * const msdc2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "univpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "mainpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "univpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "mainpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "mmpll_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "mmpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const char * const eth_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "mainpll_d40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "univpll_d24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "univpll_d20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "mainpll_d20"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const char * const vdec_mm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "univpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "mainpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "univpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "mainpll_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const char * const dpi0_mm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "lvdspll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "lvdspll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "lvdspll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "lvdspll_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const char * const dpi1_mm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "tvdpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "tvdpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "tvdpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "tvdpll_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const char * const axi_mfg_in_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "mainpll_d11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) "univpll_d24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "mmpll380m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const char * const slow_mfg_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "univpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "univpll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const char * const aud1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "apll1_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const char * const aud2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "apll2_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const char * const aud_engen1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "rg_apll1_d2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "rg_apll1_d4_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "rg_apll1_d8_en"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const char * const aud_engen2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "rg_apll2_d2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "rg_apll2_d4_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "rg_apll2_d8_en"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const char * const i2c_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "univpll_d20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "univpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "univpll_d12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const char * const aud_i2s0_m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "rg_aud1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "rg_aud2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const char * const pwm_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "univpll_d12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const char * const spi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "univpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "univpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "univpll_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const char * const aud_spdifin_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "univpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const char * const uart2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "univpll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const char * const bsi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "mainpll_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "mainpll_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) "mainpll_d20"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const char * const dbg_atclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "mainpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "univpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const char * const csw_nfiecc_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "mainpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "mainpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) "mainpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const char * const nfiecc_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "nfi2x_pad_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) "mainpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) "csw_nfiecc_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static struct mtk_composite top_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* CLK_MUX_SEL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 0x000, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MUX(CLK_TOP_GFMUX_EMI1X_SEL, "gfmux_emi1x_sel", gfmux_emi1x_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0x000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MUX(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel", emi_ddrphy_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0x000, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0x000, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 0x000, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0x000, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MUX(CLK_TOP_CAMTG_MM_SEL, "camtg_mm_sel", camtg_mm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0x000, 15, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x000, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0x000, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x000, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MUX(CLK_TOP_SPM_52M_SEL, "spm_52m_sel", spm_52m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0x000, 23, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0x000, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0x000, 26, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 0x000, 27, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* CLK_MUX_SEL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0x004, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 0x004, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MUX(CLK_TOP_MFG_MM_SEL, "mfg_mm_sel", mfg_mm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0x004, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 0x004, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MUX(CLK_TOP_SMI_MM_SEL, "smi_mm_sel", smi_mm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0x004, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 0x004, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MUX(CLK_TOP_SCAM_MM_SEL, "scam_mm_sel", scam_mm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 0x004, 23, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* CLK_MUX_SEL8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 0x040, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0x040, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 0x040, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MUX(CLK_TOP_VDEC_MM_SEL, "vdec_mm_sel", vdec_mm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0x040, 9, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MUX(CLK_TOP_DPI0_MM_SEL, "dpi0_mm_sel", dpi0_mm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0x040, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MUX(CLK_TOP_DPI1_MM_SEL, "dpi1_mm_sel", dpi1_mm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 0x040, 15, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MUX(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 0x040, 18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MUX(CLK_TOP_SLOW_MFG_SEL, "slow_mfg_sel", slow_mfg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 0x040, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 0x040, 22, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 0x040, 23, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 0x040, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 0x040, 26, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 0x040, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* CLK_SEL_9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 0x044, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 0x044, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0x044, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0x044, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 0x044, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 0x044, 17, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0x044, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* CLK_MUX_SEL13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 0x07c, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 0x07c, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 0x07c, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 0x07c, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 0x07c, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 0x07c, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 0x07c, 10, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 0x07c, 13, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static const char * const ifr_mux1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "clk26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) "armpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) "univpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "mainpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const char * const ifr_eth_25m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) "eth_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "rg_eth"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const char * const ifr_i2c0_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "ahb_infra_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) "rg_i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const struct mtk_composite ifr_muxes[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .div_reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .div_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .div_width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const struct mtk_clk_divider top_adj_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 0x0048, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 0x0048, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 0x0048, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 0x0048, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 0x004c, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 0x004c, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 0x004c, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 0x004c, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 0x0078, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .div_reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .div_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .div_width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .clk_divider_flags = _flag, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const struct mtk_clk_divider apmixed_adj_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const struct mtk_gate_regs top0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .set_ofs = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .clr_ofs = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .sta_ofs = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const struct mtk_gate_regs top1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .set_ofs = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .clr_ofs = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .sta_ofs = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const struct mtk_gate_regs top2_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .set_ofs = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .clr_ofs = 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .sta_ofs = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const struct mtk_gate_regs top3_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .set_ofs = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .clr_ofs = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .sta_ofs = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const struct mtk_gate_regs top4_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .set_ofs = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .clr_ofs = 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .sta_ofs = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const struct mtk_gate_regs top5_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .set_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .clr_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .sta_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define GATE_TOP0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .regs = &top0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define GATE_TOP0_I(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .regs = &top0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define GATE_TOP1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .regs = &top1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define GATE_TOP2(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .regs = &top2_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define GATE_TOP2_I(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .regs = &top2_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define GATE_TOP3(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .regs = &top3_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define GATE_TOP4_I(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .regs = &top4_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define GATE_TOP5(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .regs = &top5_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .ops = &mtk_clk_gate_ops_no_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const struct mtk_gate top_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* TOP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mm_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) GATE_TOP0_I(CLK_TOP_MIPI_26M_DBG, "mipi_26m_dbg", "mipi_26m", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) GATE_TOP0(CLK_TOP_SCAM_MM, "scam_mm", "scam_mm_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) GATE_TOP0(CLK_TOP_SMI_MM, "smi_mm", "smi_mm_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* TOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* TOP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) GATE_TOP2(CLK_TOP_26M_HDMI_SIFM, "hdmi_sifm_26m", "clk26m_ck", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) GATE_TOP2(CLK_TOP_26M_CEC, "cec_26m", "clk26m_ck", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) GATE_TOP2(CLK_TOP_32K_CEC, "cec_32k", "clk32k", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) GATE_TOP2(CLK_TOP_GCPU_B, "gcpu_b", "ahb_infra_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* TOP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) GATE_TOP3(CLK_TOP_RG_VDEC, "rg_vdec", "vdec_mm_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) GATE_TOP3(CLK_TOP_RG_FDPI0, "rg_fdpi0", "dpi0_mm_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) GATE_TOP3(CLK_TOP_RG_FDPI1, "rg_fdpi1", "dpi1_mm_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) GATE_TOP3(CLK_TOP_RG_AXI_MFG, "rg_axi_mfg", "axi_mfg_in_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) GATE_TOP3(CLK_TOP_RG_SLOW_MFG, "rg_slow_mfg", "slow_mfg_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* TOP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* TOP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static void __init mtk_topckgen_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) clk_data = mtk_alloc_clk_data(MT8167_CLK_TOP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) &mt8167_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) base, &mt8167_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static void __init mtk_infracfg_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) &mt8167_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define MT8167_PLL_FMAX (2500UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define CON0_MT8167_RST_BAR BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) _pcw_shift, _div_table) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .pwr_reg = _pwr_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .en_mask = _en_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .rst_bar_mask = CON0_MT8167_RST_BAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .fmax = MT8167_PLL_FMAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .pcwbits = _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .pd_reg = _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .tuner_reg = _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .pcw_reg = _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .pcw_shift = _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .div_table = _div_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) _pcw_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const struct mtk_pll_div_table mmpll_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) { .div = 0, .freq = MT8167_PLL_FMAX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) { .div = 1, .freq = 1000000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) { .div = 2, .freq = 604500000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) { .div = 3, .freq = 253500000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) { .div = 4, .freq = 126750000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) { } /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static const struct mtk_pll_data plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) 21, 0x0104, 24, 0, 0x0104, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0x00000001, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0x00000001, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) 31, 0x0180, 1, 0x0194, 0x0184, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0x00000001, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) 31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0x00000001, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) 21, 0x01C4, 24, 0, 0x01C4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0x00000001, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) 21, 0x01E4, 24, 0, 0x01E4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static void __init mtk_apmixedsys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) clk_data = mtk_alloc_clk_data(MT8167_CLK_APMIXED_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) mtk_clk_register_dividers(apmixed_adj_divs, ARRAY_SIZE(apmixed_adj_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) base, &mt8167_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8167-apmixedsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mtk_apmixedsys_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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