Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2020 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (c) 2020 BayLibre, SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *         Fabien Parent <fparent@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/mt8167-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct mtk_gate_regs vdec0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.set_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.clr_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct mtk_gate_regs vdec1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	.set_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	.clr_ofs = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.sta_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GATE_VDEC0_I(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		.regs = &vdec0_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GATE_VDEC1_I(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		.regs = &vdec1_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct mtk_gate vdec_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	/* VDEC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	GATE_VDEC0_I(CLK_VDEC_CKEN, "vdec_cken", "rg_vdec", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	/* VDEC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void __init mtk_vdecsys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 			__func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8167-vdecsys", mtk_vdecsys_init);