^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2020 BayLibre, SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Fabien Parent <fparent@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/mt8167-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct mtk_gate_regs mm0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .set_ofs = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .clr_ofs = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .sta_ofs = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct mtk_gate_regs mm1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .set_ofs = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .clr_ofs = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .sta_ofs = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GATE_MM0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .regs = &mm0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GATE_MM1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .regs = &mm1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct mtk_gate mm_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* MM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "smi_mm", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "smi_mm", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GATE_MM0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "smi_mm", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "smi_mm", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "smi_mm", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "smi_mm", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GATE_MM0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "smi_mm", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "smi_mm", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "smi_mm", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "smi_mm", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GATE_MM0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "smi_mm", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "smi_mm", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "smi_mm", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "smi_mm", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "smi_mm", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "smi_mm", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "smi_mm", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* MM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GATE_MM1(CLK_MM_DISP_PWM_MM, "mm_disp_pwm_mm", "smi_mm", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GATE_MM1(CLK_MM_DISP_PWM_26M, "mm_disp_pwm_26m", "smi_mm", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GATE_MM1(CLK_MM_DSI_ENGINE, "mm_dsi_engine", "smi_mm", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GATE_MM1(CLK_MM_DSI_DIGITAL, "mm_dsi_digital", "dsi0_lntc_dsick", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GATE_MM1(CLK_MM_DPI0_ENGINE, "mm_dpi0_engine", "smi_mm", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GATE_MM1(CLK_MM_DPI0_PXL, "mm_dpi0_pxl", "rg_fdpi0", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) GATE_MM1(CLK_MM_LVDS_PXL, "mm_lvds_pxl", "vpll_dpix", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx_dig_cts", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "smi_mm", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) GATE_MM1(CLK_MM_DPI1_PXL, "mm_dpi1_pxl", "rg_fdpi1", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) GATE_MM1(CLK_MM_HDMI_PXL, "mm_hdmi_pxl", "rg_fdpi1", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll12_div6", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) GATE_MM1(CLK_MM_HDMI_ADSP_BCK, "mm_hdmi_adsp_b", "apll12_div4b", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk_mt8167_mm_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const struct mtk_gate *gates_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int gates_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct clk_mt8167_mm_driver_data mt8167_mmsys_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .gates_clk = mm_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .gates_num = ARRAY_SIZE(mm_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int clk_mt8167_mm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct device_node *node = dev->parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct clk_mt8167_mm_driver_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) data = &mt8167_mmsys_driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct platform_driver clk_mt8173_mm_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "clk-mt8167-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .probe = clk_mt8167_mm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) builtin_platform_driver(clk_mt8173_mm_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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