^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/mt8135-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static DEFINE_SPINLOCK(mt8135_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct mtk_fixed_factor top_divs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char * const axi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "syspll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "syspll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "syspll_d3p5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const char * const smi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "clkph_mck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "syspll_d2p5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "syspll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "univpll1_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "mmpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "mmpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "mmpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "mmpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "vdecpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "lvdspll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const char * const mfg_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "syspll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "syspll_d2p5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "mmpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "mmpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "mmpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "mmpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "mmpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "mmpll_d7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const char * const irda_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "univpll1_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const char * const cam_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "syspll_d3p5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "syspll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "univpll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const char * const aud_intbus_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "syspll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "univpll_d10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const char * const jpg_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "syspll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "univpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const char * const disp_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "syspll_d3p5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "lvdspll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "vdecpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const char * const msdc30_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "syspll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "msdcpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const char * const usb20_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "univpll2_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "univpll1_d10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const char * const venc_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "syspll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "univpll1_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "mmpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "mmpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "mmpll_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const char * const spi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "syspll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "syspll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "syspll_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "univpll1_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "univpll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const char * const uart_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const char * const mem_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "clkph_mck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const char * const camtg_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "univpll1_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "syspll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "syspll_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const char * const audio_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "syspll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const char * const fix_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "rtc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "univpll1_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "univpll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const char * const vdec_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "vdecpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "clkph_mck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "syspll_d2p5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "syspll_d3p5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "syspll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "syspll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "syspll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "univpll_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "lvdspll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const char * const ddrphycfg_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "axi_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "syspll_d12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const char * const dpilvds_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "lvdspll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "lvdspll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "lvdspll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "lvdspll_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const char * const pmicspi_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "univpll2_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "syspll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "syspll_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "univpll1_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "mempll_mck_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "syspll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const char * const smi_mfg_as_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "smi_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "mfg_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "mem_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const char * const gcpu_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "syspll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "syspll_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const char * const dpi1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "tvhdmi_h_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "tvhdmi_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "tvhdmi_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const char * const cci_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "mainpll_537p3m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "syspll_d2p5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "syspll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const char * const apll_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "apll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "apll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "apll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "apll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "apll_d24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const char * const hdmipll_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "hdmitx_clkdig_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "hdmitx_clkdig_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "hdmitx_clkdig_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct mtk_composite top_muxes[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* CLK_CFG_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* CLK_CFG_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0x0144, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* CLK_CFG_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* CLK_CFG_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* CLK_CFG_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* CLK_CFG_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* CLK_CFG_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0x015c, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* CLK_CFG_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x0164, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* CLK_CFG_9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const struct mtk_gate_regs infra_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .set_ofs = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .clr_ofs = 0x0044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .sta_ofs = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define GATE_ICG(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .regs = &infra_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct mtk_gate infra_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct mtk_gate_regs peri0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .set_ofs = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .clr_ofs = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .sta_ofs = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct mtk_gate_regs peri1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .set_ofs = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .clr_ofs = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .sta_ofs = 0x001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define GATE_PERI0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .regs = &peri0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define GATE_PERI1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .regs = &peri1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct mtk_gate peri_gates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* PERI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* PERI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const char * const uart_ck_sel_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "uart_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const struct mtk_composite peri_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void __init mtk_topckgen_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &mt8135_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void __init mtk_infrasys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) mtk_register_reset_controller(node, 2, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static void __init mtk_pericfg_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) &mt8135_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mtk_register_reset_controller(node, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define MT8135_PLL_FMAX (2000 * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define CON0_MT8135_RST_BAR BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .pwr_reg = _pwr_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .en_mask = _en_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .rst_bar_mask = CON0_MT8135_RST_BAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .fmax = MT8135_PLL_FMAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .pcwbits = _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .pd_reg = _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .tuner_reg = _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .pcw_reg = _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .pcw_shift = _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const struct mtk_pll_data plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static void __init mtk_apmixedsys_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mtk_apmixedsys_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags