^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-cpumux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/mt7629-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MT7629_PLL_FMAX (2500UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CON0_MT7629_RST_BAR BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) _pcw_shift, _div_table, _parent_name) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .pwr_reg = _pwr_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .en_mask = _en_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .rst_bar_mask = CON0_MT7629_RST_BAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .fmax = MT7629_PLL_FMAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .pcwbits = _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .pd_reg = _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .tuner_reg = _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .pcw_reg = _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .pcw_shift = _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .div_table = _div_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .parent_name = _parent_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) _pcw_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) NULL, "clk20m")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GATE_APMIXED(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .regs = &apmixed_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GATE_INFRA(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .regs = &infra_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GATE_PERI0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .regs = &peri0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GATE_PERI1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .regs = &peri1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static DEFINE_SPINLOCK(mt7629_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const char * const axi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "dmpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char * const mem_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "dmpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const char * const ddrphycfg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "syspll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const eth_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "sgmiipll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "dmpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const char * const pwm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const char * const f10m_ref_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "sgmiipll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const char * const nfi_infra_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "syspll_d7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const char * const flash_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "univpll_d80_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "syspll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const char * const uart_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const char * const spi0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "clkxtal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const char * const spi1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "syspll4_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "clkxtal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const char * const msdc30_0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "univpll2_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "univ48m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const char * const msdc30_1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "univpll2_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "univ48m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "univpll2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const char * const ap2wbmcu_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "univ48m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "univpll2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const char * const audio_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "syspll4_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "syspll1_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const char * const aud_intbus_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "dmpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const char * const pmicspi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "syspll1_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "dmpll_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const char * const scp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const char * const atb_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "syspll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const char * const hif_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "univpll_d7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const char * const sata_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const char * const usb20_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "syspll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const char * const aud1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "clkxtal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const char * const irrx_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "syspll4_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const char * const crypto_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "syspll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const char * const gpt10m_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "clkxtal_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const char * const peribus_ck_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "syspll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const char * const infra_mux1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "armpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "main_core_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "armpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct mtk_gate_regs apmixed_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .set_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .clr_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .sta_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct mtk_gate_regs infra_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .set_ofs = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .clr_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .sta_ofs = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct mtk_gate_regs peri0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .set_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .clr_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .sta_ofs = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const struct mtk_gate_regs peri1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .set_ofs = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .clr_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .sta_ofs = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct mtk_pll_data plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0, 21, 0x0204, 24, 0, 0x0204, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0, 21, 0x0300, 1, 0, 0x0304, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0, 21, 0x0314, 1, 0, 0x0318, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0, 21, 0x0358, 1, 0, 0x035C, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct mtk_gate apmixed_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct mtk_gate infra_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "hd_faxi", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) GATE_INFRA(CLK_INFRA_TRNG_PD, "infra_trng_pd", "hd_faxi", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GATE_INFRA(CLK_INFRA_DEVAPC_PD, "infra_devapc_pd", "hd_faxi", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "infrao_10m", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) GATE_INFRA(CLK_INFRA_SEJ_PD, "infra_sej_pd", "infrao_10m", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct mtk_fixed_clk top_fixed_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 31250000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 31250000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 125000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 125000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 250000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 250000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 33333333),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct mtk_fixed_factor top_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) FACTOR(CLK_TOP_PWM_QTR_26M, "pwm_qtr_26m", "clkxtal", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "cpum_tck", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) FACTOR(CLK_TOP_TO_USB3_DA_TOP, "to_usb3_da_top", "clkxtal", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "mempll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "mempll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) FACTOR(CLK_TOP_CLKXTAL_D4, "clkxtal_d4", "clkxtal", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) FACTOR(CLK_TOP_HD_FAXI, "hd_faxi", "axi_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) FACTOR(CLK_TOP_FAXI, "faxi", "axi_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) FACTOR(CLK_TOP_F_FAUD_INTBUS, "f_faud_intbus", "aud_intbus_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) FACTOR(CLK_TOP_AP2WBHIF_HCLK, "ap2wbhif_hclk", "syspll1_d8", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) FACTOR(CLK_TOP_10M_INFRAO, "infrao_10m", "gpt10m_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) FACTOR(CLK_TOP_MSDC30_1, "msdc30_1", "msdc30_1_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) FACTOR(CLK_TOP_SPI, "spi", "spi0_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) FACTOR(CLK_TOP_SF, "sf", "nfi_infra_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) FACTOR(CLK_TOP_FLASH, "flash", "flash_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "sata_sel", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) FACTOR(CLK_TOP_TO_USB3_MCU, "to_usb3_mcu", "axi_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const struct mtk_gate peri_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* PERI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* PERI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static struct mtk_composite infra_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* INFRA_TOPCKGEN_CKMUXSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct mtk_composite top_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* CLK_CFG_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 0x040, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 0x040, 8, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 0x040, 16, 1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 0x040, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* CLK_CFG_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 0x050, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 0x050, 8, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 0x050, 16, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 0x050, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* CLK_CFG_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 0x060, 0, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 0x060, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 0x060, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 0x060, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* CLK_CFG_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0x070, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 0x070, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MUX_GATE(CLK_TOP_AP2WBMCU_SEL, "ap2wbmcu_sel", ap2wbmcu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 0x070, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MUX_GATE(CLK_TOP_AP2WBHIF_SEL, "ap2wbhif_sel", ap2wbmcu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 0x070, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* CLK_CFG_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 0x080, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0x080, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0x080, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0x080, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* CLK_CFG_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 0x090, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 0x090, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MUX_GATE(CLK_TOP_SATA_SEL, "sata_sel", sata_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 0x090, 16, 1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 0x090, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* CLK_CFG_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x0A0, 0, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0x0A0, 8, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", irrx_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0x0A0, 16, 1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0x0A0, 24, 1, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* CLK_CFG_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MUX_GATE(CLK_TOP_SATA_MCU_SEL, "sata_mcu_sel", scp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 0x0B0, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0x0B0, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, "pcie1_mcu_sel", scp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 0x0B0, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, "ssusb_mcu_sel", scp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0x0B0, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* CLK_CFG_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MUX_GATE(CLK_TOP_CRYPTO_SEL, "crypto_sel", crypto_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0x0C0, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, "sgmii_ref_1_sel", f10m_ref_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 0x0C0, 8, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MUX_GATE(CLK_TOP_10M_SEL, "gpt10m_sel", gpt10m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 0x0C0, 16, 1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static struct mtk_composite peri_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* PERI_GLOBALCON_CKSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int mtk_topckgen_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) base, &mt7629_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int mtk_infrasys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return of_clk_add_provider(node, of_clk_src_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int mtk_pericfg_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) &mt7629_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int mtk_apmixedsys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mtk_clk_register_gates(node, apmixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ARRAY_SIZE(apmixed_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const struct of_device_id of_match_clk_mt7629[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .compatible = "mediatek,mt7629-apmixedsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .data = mtk_apmixedsys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .compatible = "mediatek,mt7629-infracfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .data = mtk_infrasys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .compatible = "mediatek,mt7629-topckgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .data = mtk_topckgen_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .compatible = "mediatek,mt7629-pericfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .data = mtk_pericfg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static int clk_mt7629_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int (*clk_init)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) clk_init = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (!clk_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) r = clk_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct platform_driver clk_mt7629_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .probe = clk_mt7629_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .name = "clk-mt7629",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .of_match_table = of_match_clk_mt7629,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int clk_mt7629_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return platform_driver_register(&clk_mt7629_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) arch_initcall(clk_mt7629_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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