^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/mt7629-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GATE_PCIE(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .regs = &pcie_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GATE_SSUSB(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .regs = &ssusb_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct mtk_gate_regs pcie_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .set_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .clr_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .sta_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct mtk_gate_regs ssusb_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .set_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .clr_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .sta_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct mtk_gate ssusb_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "to_u2_phy_1p", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct mtk_gate pcie_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mtk_register_reset_controller(node, 1, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int clk_mt7629_pciesys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mtk_register_reset_controller(node, 1, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct of_device_id of_match_clk_mt7629_hif[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .compatible = "mediatek,mt7629-pciesys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .data = clk_mt7629_pciesys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .compatible = "mediatek,mt7629-ssusbsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .data = clk_mt7629_ssusbsys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int clk_mt7629_hif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int (*clk_init)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_init = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!clk_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) r = clk_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct platform_driver clk_mt7629_hif_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .probe = clk_mt7629_hif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = "clk-mt7629-hif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .of_match_table = of_match_clk_mt7629_hif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) builtin_platform_driver(clk_mt7629_hif_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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