^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/mt7629-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GATE_ETH(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .regs = ð_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct mtk_gate_regs eth_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .set_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .clr_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .sta_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct mtk_gate eth_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct mtk_gate_regs sgmii_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .set_ofs = 0xE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .clr_ofs = 0xE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .sta_ofs = 0xE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GATE_SGMII(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .regs = &sgmii_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct mtk_gate sgmii_clks[2][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "ssusb_tx250m", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "ssusb_eq_rx250m", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "ssusb_cdr_ref", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "ssusb_cdr_fb", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "ssusb_tx250m", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "ssusb_eq_rx250m", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "ssusb_cdr_ref", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "ssusb_cdr_fb", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int clk_mt7629_ethsys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mtk_register_reset_controller(node, 1, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct of_device_id of_match_clk_mt7629_eth[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .compatible = "mediatek,mt7629-ethsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .data = clk_mt7629_ethsys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .compatible = "mediatek,mt7629-sgmiisys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .data = clk_mt7629_sgmiisys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int clk_mt7629_eth_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int (*clk_init)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk_init = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!clk_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) r = clk_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct platform_driver clk_mt7629_eth_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .probe = clk_mt7629_eth_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "clk-mt7629-eth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .of_match_table = of_match_clk_mt7629_eth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) builtin_platform_driver(clk_mt7629_eth_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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