^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chen Zhong <chen.zhong@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-cpumux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/mt7622-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h> /* for consumer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MT7622_PLL_FMAX (2500UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CON0_MT7622_RST_BAR BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) _pcw_shift, _div_table, _parent_name) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .pwr_reg = _pwr_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .en_mask = _en_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .rst_bar_mask = CON0_MT7622_RST_BAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .fmax = MT7622_PLL_FMAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .pcwbits = _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .pd_reg = _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .tuner_reg = _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .pcw_reg = _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .pcw_shift = _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .div_table = _div_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .parent_name = _parent_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) _pcw_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) NULL, "clkxtal")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GATE_APMIXED(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .regs = &apmixed_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GATE_INFRA(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .regs = &infra_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GATE_TOP0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .regs = &top0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .ops = &mtk_clk_gate_ops_no_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GATE_TOP1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .regs = &top1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .ops = &mtk_clk_gate_ops_no_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GATE_PERI0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .regs = &peri0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GATE_PERI1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .regs = &peri1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static DEFINE_SPINLOCK(mt7622_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const char * const infra_mux1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "armpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "main_core_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "armpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const char * const axi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "univpll_d7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const char * const mem_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "dmpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const char * const ddrphycfg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "syspll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const char * const eth_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "univpll_d7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const char * const pwm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const char * const f10m_ref_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "syspll4_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const char * const nfi_infra_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "syspll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const char * const flash_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "univpll_d80_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "syspll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const char * const uart_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const char * const spi0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "clkxtal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const char * const spi1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "syspll4_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "clkxtal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const char * const msdc30_0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "univpll2_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "univ48m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const char * const a1sys_hp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "aud1pll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "aud2pll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "clkxtal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const char * const intdir_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "syspll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "sgmiipll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const char * const aud_intbus_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "syspll3_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const char * const pmicspi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "clk_null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "univpll2_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const char * const atb_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "syspll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const char * const audio_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "syspll4_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "univpll1_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const char * const usb20_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "clkxtal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const char * const aud1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "aud1pll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const char * const aud2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "aud2pll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const char * const asm_l_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const char * const apll1_ck_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "aud1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "aud2_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const char * const peribus_ck_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "syspll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct mtk_gate_regs apmixed_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .set_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .clr_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .sta_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct mtk_gate_regs infra_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .set_ofs = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .clr_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .sta_ofs = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct mtk_gate_regs top0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .set_ofs = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .clr_ofs = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .sta_ofs = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct mtk_gate_regs top1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .set_ofs = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .clr_ofs = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .sta_ofs = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct mtk_gate_regs peri0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .set_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .clr_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .sta_ofs = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct mtk_gate_regs peri1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .set_ofs = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .clr_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .sta_ofs = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct mtk_pll_data plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0, 21, 0x0300, 1, 0, 0x0304, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0, 21, 0x0314, 1, 0, 0x0318, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0, 31, 0x0324, 1, 0, 0x0328, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0, 31, 0x0334, 1, 0, 0x0338, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0, 21, 0x0344, 1, 0, 0x0348, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0, 21, 0x0358, 1, 0, 0x035C, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const struct mtk_gate apmixed_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct mtk_gate infra_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct mtk_fixed_clk top_fixed_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 31250000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 31250000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 125000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 125000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 250000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 250000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 33333333),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct mtk_fixed_factor top_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const struct mtk_gate top_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* TOP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* TOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct mtk_clk_divider top_adj_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0x120, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 0x120, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 0x124, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 0x124, 8, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 0x124, 16, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 0x124, 24, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 0x128, 8, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 0x128, 24, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct mtk_gate peri_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* PERI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* PERI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static struct mtk_composite infra_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 0x000, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static struct mtk_composite top_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* CLK_CFG_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 0x040, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0x040, 8, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 0x040, 16, 1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 0x040, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* CLK_CFG_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0x050, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0x050, 8, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0x050, 16, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 0x050, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* CLK_CFG_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0x060, 0, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x060, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0x060, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x060, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* CLK_CFG_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0x070, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0x070, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 0x070, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0x070, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* CLK_CFG_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 0x080, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 0x080, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0x080, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 0x080, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* CLK_CFG_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 0x090, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 0x090, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0x090, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 0x090, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* CLK_CFG_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0x0A0, 0, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 0x0A0, 8, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 0x0A0, 16, 1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 0x0A0, 24, 1, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* CLK_CFG_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 0x0B0, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 0x0B0, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 0x0B0, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* CLK_AUDDIV_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 0x120, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 0x120, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 0x120, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 0x120, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 0x120, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 0x120, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct mtk_composite peri_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* PERI_GLOBALCON_CKSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int mtk_topckgen_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) base, &mt7622_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) base, &mt7622_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int mtk_infrasys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) r = of_clk_add_provider(node, of_clk_src_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) mtk_register_reset_controller(node, 1, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int mtk_apmixedsys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mtk_clk_register_gates(node, apmixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ARRAY_SIZE(apmixed_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int mtk_pericfg_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) &mt7622_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mtk_register_reset_controller(node, 2, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const struct of_device_id of_match_clk_mt7622[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .compatible = "mediatek,mt7622-apmixedsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .data = mtk_apmixedsys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .compatible = "mediatek,mt7622-infracfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .data = mtk_infrasys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .compatible = "mediatek,mt7622-topckgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .data = mtk_topckgen_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .compatible = "mediatek,mt7622-pericfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .data = mtk_pericfg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static int clk_mt7622_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int (*clk_init)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) clk_init = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (!clk_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) r = clk_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static struct platform_driver clk_mt7622_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .probe = clk_mt7622_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .name = "clk-mt7622",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .of_match_table = of_match_clk_mt7622,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int clk_mt7622_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return platform_driver_register(&clk_mt7622_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) arch_initcall(clk_mt7622_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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