^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chen Zhong <chen.zhong@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/mt7622-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GATE_ETH(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .regs = ð_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct mtk_gate_regs eth_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .set_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .clr_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .sta_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct mtk_gate eth_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct mtk_gate_regs sgmii_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .set_ofs = 0xE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .clr_ofs = 0xE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .sta_ofs = 0xE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GATE_SGMII(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .regs = &sgmii_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct mtk_gate sgmii_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "ssusb_tx250m", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "ssusb_eq_rx250m", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "ssusb_cdr_ref", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "ssusb_cdr_fb", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int clk_mt7622_ethsys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mtk_register_reset_controller(node, 1, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct of_device_id of_match_clk_mt7622_eth[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .compatible = "mediatek,mt7622-ethsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .data = clk_mt7622_ethsys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .compatible = "mediatek,mt7622-sgmiisys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .data = clk_mt7622_sgmiisys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int clk_mt7622_eth_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int (*clk_init)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk_init = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!clk_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) r = clk_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct platform_driver clk_mt7622_eth_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .probe = clk_mt7622_eth_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .name = "clk-mt7622-eth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .of_match_table = of_match_clk_mt7622_eth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) builtin_platform_driver(clk_mt7622_eth_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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