Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Chen Zhong <chen.zhong@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	   Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <dt-bindings/clock/mt7622-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define GATE_AUDIO0(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		.regs = &audio0_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.ops = &mtk_clk_gate_ops_no_setclr,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define GATE_AUDIO1(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		.regs = &audio1_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.ops = &mtk_clk_gate_ops_no_setclr,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define GATE_AUDIO2(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.regs = &audio2_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.ops = &mtk_clk_gate_ops_no_setclr,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define GATE_AUDIO3(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.regs = &audio3_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.ops = &mtk_clk_gate_ops_no_setclr,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static const struct mtk_gate_regs audio0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.set_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.clr_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const struct mtk_gate_regs audio1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.set_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.clr_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.sta_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const struct mtk_gate_regs audio2_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.set_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.clr_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.sta_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static const struct mtk_gate_regs audio3_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.set_ofs = 0x634,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.clr_ofs = 0x634,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.sta_ofs = 0x634,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static const struct mtk_gate audio_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* AUDIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* AUDIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* AUDIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* AUDIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int clk_mt7622_audiosys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			       clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			"could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		goto err_clk_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	r = devm_of_platform_populate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		goto err_plat_populate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) err_plat_populate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	of_clk_del_provider(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) err_clk_provider:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct of_device_id of_match_clk_mt7622_aud[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.compatible = "mediatek,mt7622-audsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.data = clk_mt7622_audiosys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		/* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int clk_mt7622_aud_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int (*clk_init)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	clk_init = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (!clk_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	r = clk_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			"could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct platform_driver clk_mt7622_aud_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.probe = clk_mt7622_aud_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.name = "clk-mt7622-aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.of_match_table = of_match_clk_mt7622_aud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) builtin_platform_driver(clk_mt7622_aud_drv);