^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/mt6797-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * For some clocks, we don't care what their actual rates are. And these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * clocks may change their rate on different products or different scenarios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * So we model these clocks' rate as 0, to denote it's not an actual rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static DEFINE_SPINLOCK(mt6797_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct mtk_fixed_factor top_fixed_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char * const axi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "ulposc_axi_ck_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const char * const ulposc_axi_ck_mux_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "ulposc_axi_ck_mux_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const char * const ulposc_axi_ck_mux_pre_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "ulposc_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "ulposc_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char * const ddrphycfg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const mm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "imgpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char * const pwm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "ulposc_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "ulposc_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "ulposc_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "ulposc_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "ulposc_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const char * const vdec_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "vdecpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "imgpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const char * const venc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "codecpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const char * const mfg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "mfgpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const char * const camtg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const char * const uart_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const char * const spi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "ulposc_spi_ck_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const char * const ulposc_spi_ck_mux_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "ulposc_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "ulposc_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const char * const usb20_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const char * const msdc50_0_hclk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const char * const msdc50_0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "msdcpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "msdcpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const char * const msdc30_1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "msdcpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const char * const msdc30_2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "syspll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "msdcpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const char * const audio_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "syspll4_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "syspll1_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const char * const aud_intbus_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const char * const pmicspi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "ulposc_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "ulposc_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "syspll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const char * const scp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "ulposc_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const char * const atb_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const char * const mjc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "imgpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const char * const dpi0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "tvdpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "tvdpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "tvdpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "tvdpll_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const char * const aud_1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "apll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const char * const aud_2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "apll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const char * const ssusb_top_sys_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const char * const spm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const char * const bsi_spi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "syspll_d3_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const char * const audio_h_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "apll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "apll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const char * const mfg_52m_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const char * const anc_md32_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Clock mux ddrphycfg is needed by the DRAM controller. We mark it as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * critical as otherwise the system will hang after boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct mtk_composite top_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 0x0040, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0x0040, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ulposc_spi_ck_mux_parents, 0x0060, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0x0060, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) msdc50_0_hclk_parents, 0x0070, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0x0070, 16, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0x0070, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0x0080, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0x0080, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0x0080, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 0x0090, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0x0090, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 0x0090, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0x00A0, 16, 1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0x00A0, 24, 1, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ssusb_top_sys_parents, 0x00B0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0x00C0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MUX(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0x00C0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x00C0, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0x00C0, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MUX(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0x0104, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int mtk_topckgen_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) &mt6797_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct mtk_gate_regs infra0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .set_ofs = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .clr_ofs = 0x0084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .sta_ofs = 0x0090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const struct mtk_gate_regs infra1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .set_ofs = 0x0088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .clr_ofs = 0x008c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .sta_ofs = 0x0094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const struct mtk_gate_regs infra2_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .set_ofs = 0x00a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .clr_ofs = 0x00ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .sta_ofs = 0x00b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define GATE_ICG0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .regs = &infra0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define GATE_ICG1(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .regs = &infra1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define GATE_ICG2(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .regs = &infra2_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Clock gates dramc and dramc_b are needed by the DRAM controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * We mark them as critical as otherwise the system will hang after boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static const struct mtk_gate infra_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "axi_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "axi_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) "clk26m", 31, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "clk26m", 11, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "ssusb_top_sys_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "clk26m", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "axi_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const struct mtk_fixed_factor infra_fixed_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct clk_onecell_data *infra_clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void mtk_infrasys_init_early(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!infra_clk_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for (i = 0; i < CLK_INFRA_NR; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) infra_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mtk_infrasys_init_early);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int mtk_infrasys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (!infra_clk_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) for (i = 0; i < CLK_INFRA_NR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) infra_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) infra_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define MT6797_PLL_FMAX (3000UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define CON0_MT6797_RST_BAR BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) _pcw_shift, _div_table) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .pwr_reg = _pwr_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .en_mask = _en_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .rst_bar_mask = CON0_MT6797_RST_BAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .fmax = MT6797_PLL_FMAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .pcwbits = _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .pd_reg = _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .tuner_reg = _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .pcw_reg = _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .pcw_shift = _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .div_table = _div_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) _pcw_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const struct mtk_pll_data plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 21, 0x220, 4, 0x0, 0x224, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 0x230, 4, 0x0, 0x234, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 0x244, 24, 0x0, 0x244, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 0x250, 4, 0x0, 0x254, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 0x260, 4, 0x0, 0x264, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 0x270, 4, 0x0, 0x274, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 0x290, 4, 0x0, 0x294, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 0x2E4, 4, 0x0, 0x2E8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 0x2A0, 4, 0x2A8, 0x2A4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 0x2B4, 4, 0x2BC, 0x2B8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int mtk_apmixedsys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const struct of_device_id of_match_clk_mt6797[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .compatible = "mediatek,mt6797-topckgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .data = mtk_topckgen_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .compatible = "mediatek,mt6797-infracfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .data = mtk_infrasys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .compatible = "mediatek,mt6797-apmixedsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .data = mtk_apmixedsys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int clk_mt6797_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int (*clk_init)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) clk_init = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (!clk_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) r = clk_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static struct platform_driver clk_mt6797_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .probe = clk_mt6797_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .name = "clk-mt6797",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .of_match_table = of_match_clk_mt6797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int __init clk_mt6797_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return platform_driver_register(&clk_mt6797_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) arch_initcall(clk_mt6797_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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