Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt6797-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct mtk_gate_regs vdec0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.set_ofs = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.clr_ofs = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	.sta_ofs = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct mtk_gate_regs vdec1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.set_ofs = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.clr_ofs = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	.sta_ofs = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GATE_VDEC0(_id, _name, _parent, _shift) {		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	.id = _id,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.name = _name,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	.parent_name = _parent,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	.regs = &vdec0_cg_regs,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	.shift = _shift,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	.ops = &mtk_clk_gate_ops_setclr_inv,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GATE_VDEC1(_id, _name, _parent, _shift) {		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	.id = _id,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	.name = _name,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	.parent_name = _parent,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	.regs = &vdec1_cg_regs,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	.shift = _shift,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	.ops = &mtk_clk_gate_ops_setclr_inv,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct mtk_gate vdec_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct of_device_id of_match_clk_mt6797_vdec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	{ .compatible = "mediatek,mt6797-vdecsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int clk_mt6797_vdec_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			       clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 			"could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static struct platform_driver clk_mt6797_vdec_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	.probe = clk_mt6797_vdec_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 		.name = "clk-mt6797-vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 		.of_match_table = of_match_clk_mt6797_vdec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) builtin_platform_driver(clk_mt6797_vdec_drv);