^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/clock/mt6797-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const struct mtk_gate_regs mm0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .set_ofs = 0x0104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .clr_ofs = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .sta_ofs = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct mtk_gate_regs mm1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .set_ofs = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .clr_ofs = 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .sta_ofs = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GATE_MM0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .regs = &mm0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GATE_MM1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .regs = &mm1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const struct mtk_gate mm_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color", "mm_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc", "mm_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock", "mm_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock", "mm_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "dpi0_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "mm_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "mjc_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "mm_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "clk26m", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "clk26m", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int clk_mt6797_mm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct device_node *node = dev->parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk_data = mtk_alloc_clk_data(CLK_MM_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct platform_driver clk_mt6797_mm_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .probe = clk_mt6797_mm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "clk-mt6797-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) builtin_platform_driver(clk_mt6797_mm_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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