^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Wendell Lin <wendell.lin@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/mt6779-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static DEFINE_SPINLOCK(mt6779_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct mtk_fixed_clk top_fixed_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct mtk_fixed_factor top_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "tvdpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const char * const axi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "mainpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "osc_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const char * const mm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "tvdpll_mainpll_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "mmpll_d5_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "mainpll_d3_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const char * const scp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "univpll_d2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "ad_osc2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "osc2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "osc2_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const char * const img_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "mainpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "mainpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "mmpll_d5_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "tvdpll_mainpll_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "mainpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const char * const ipe_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "mainpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "mmpll_d5_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "mainpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const char * const dpe_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "mainpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "mmpll_d5_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "mainpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const char * const cam_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "mainpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "mmpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "mmpll_d5_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "adsppll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "tvdpll_mainpll_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "univpll_d3_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const char * const ccu_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "mainpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "mmpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "mmpll_d5_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "adsppll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "univpll_d3_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char * const dsp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "univpll_d3_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "univpll_d3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "mmpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "adsppll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "tvdpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "tvdpll_mainpll_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "adsppll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const char * const dsp1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "univpll_d3_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "univpll_d3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "mmpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "adsppll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "tvdpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "tvdpll_mainpll_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "adsppll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const char * const dsp2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "univpll_d3_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "univpll_d3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "mmpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "adsppll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "tvdpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "tvdpll_mainpll_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "adsppll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const char * const dsp3_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "univpll_d3_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "mmpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "mainpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "tvdpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "tvdpll_mainpll_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "adsppll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "mmpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const char * const ipu_if_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "univpll_d3_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "univpll_d3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "mmpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "adsppll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "tvdpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "tvdpll_mainpll_d2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "adsppll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const char * const mfg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "mfgpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "mainpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const char * const f52m_mfg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "univpll_d3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "univpll_d3_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const char * const camtg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "univpll_192m_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "univpll_d3_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "univpll_192m_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "univpll_d3_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "csw_f26m_ck_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "univpll_192m_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "univpll_192m_d32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const char * const camtg2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "univpll_192m_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "univpll_d3_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "univpll_192m_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "univpll_d3_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "csw_f26m_ck_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "univpll_192m_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "univpll_192m_d32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const char * const camtg3_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "univpll_192m_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "univpll_d3_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "univpll_192m_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "univpll_d3_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "csw_f26m_ck_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "univpll_192m_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "univpll_192m_d32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const char * const camtg4_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "univpll_192m_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "univpll_d3_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "univpll_192m_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "univpll_d3_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "csw_f26m_ck_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "univpll_192m_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "univpll_192m_d32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const char * const uart_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "univpll_d3_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const char * const spi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "mainpll_d5_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "mainpll_d3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "msdcpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const char * const msdc50_hclk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "mainpll_d3_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const char * const msdc50_0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "msdcpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "msdcpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "univpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "mainpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "univpll_d2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const char * const msdc30_1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "mainpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "mainpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "msdcpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const char * const audio_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "mainpll_d5_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "mainpll_d7_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "mainpll_d2_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const char * const aud_intbus_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "mainpll_d7_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const char * const fpwrap_ulposc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "osc_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "osc_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "osc_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "osc_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const char * const atb_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "mainpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const char * const sspm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "univpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "mainpll_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const char * const dpi0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "tvdpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "tvdpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "tvdpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "tvdpll_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const char * const scam_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "mainpll_d5_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const char * const disppwm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "univpll_d3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "osc_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "osc_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "osc_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const char * const usb_top_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "univpll_d5_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "univpll_d3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "univpll_d5_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const char * const ssusb_top_xhci_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "univpll_d5_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "univpll_d3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) "univpll_d5_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const char * const spm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "osc_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "mainpll_d2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const char * const i2c_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "mainpll_d2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "univpll_d5_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const char * const seninf_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "mmpll_d4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "mmpll_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const char * const seninf1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "mmpll_d4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "mmpll_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const char * const seninf2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) "mmpll_d4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) "mmpll_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const char * const dxcc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "mainpll_d2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const char * const aud_engen1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "apll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "apll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "apll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const char * const aud_engen2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "apll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "apll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "apll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const char * const faes_ufsfde_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "mainpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "univpll_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const char * const fufs_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) "mainpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) "mainpll_d2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) "mainpll_d2_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const char * const aud_1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "apll1_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const char * const aud_2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) "apll2_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const char * const adsp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "univpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) "mmpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) "adsppll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "adsppll_d6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static const char * const dpmaif_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "univpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "univpll_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const char * const venc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "mmpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) "mmpll_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "mainpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) "mainpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "mmpll_d4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) "univpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "mmpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) "univpll_192m_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static const char * const vdec_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) "univpll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) "mainpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) "univpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "mainpll_d2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "univpll_d5_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "mainpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "univpll_192m_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const char * const camtm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) "univpll_d3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) "univpll_d2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const char * const pwm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "univpll_d2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const char * const audio_h_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "apll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "apll2_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const char * const camtg5_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "univpll_192m_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "univpll_d3_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "univpll_192m_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "univpll_d3_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "csw_f26m_ck_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "univpll_192m_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "univpll_192m_d32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * CRITICAL CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * axi_sel is the main bus clock of whole SOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * spm_sel is the clock of the always-on co-processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * sspm_sel is the clock of the always-on co-processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const struct mtk_mux top_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* CLK_CFG_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 0x20, 0x24, 0x28, 0, 2, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 0x004, 0, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* CLK_CFG_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* CLK_CFG_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 0x40, 0x44, 0x48, 16, 4, 23, 0x004, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* CLK_CFG_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 0x50, 0x54, 0x58, 16, 2, 23, 0x004, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) f52m_mfg_parents, 0x50, 0x54, 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 24, 2, 31, 0x004, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* CLK_CFG_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 0x60, 0x64, 0x68, 0, 3, 7, 0x004, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 0x60, 0x64, 0x68, 8, 3, 15, 0x004, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* CLK_CFG_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) msdc50_hclk_parents, 0x70, 0x74, 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 16, 2, 23, 0x004, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) msdc50_0_parents, 0x70, 0x74, 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 24, 3, 31, 0x004, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* CLK_CFG_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) msdc30_1_parents, 0x80, 0x84, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 0, 3, 7, 0x004, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) aud_intbus_parents, 0x80, 0x84, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 16, 2, 23, 0x004, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) fpwrap_ulposc_parents, 0x80, 0x84, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 24, 3, 31, 0x004, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* CLK_CFG_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 0x90, 0x94, 0x98, 8, 3, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 0x004, 29, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 0x90, 0x94, 0x98, 24, 1, 31, 0x004, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* CLK_CFG_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) disppwm_parents, 0xa0, 0xa4, 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 0, 3, 7, 0x008, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) usb_top_parents, 0xa0, 0xa4, 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 8, 2, 15, 0x008, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ssusb_top_xhci_parents, 0xa0, 0xa4, 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 16, 2, 23, 0x008, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 0xa0, 0xa4, 0xa8, 24, 2, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 0x008, 4, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* CLK_CFG_9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x008, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) seninf1_parents, 0xb0, 0xb4, 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 16, 2, 23, 0x008, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) seninf2_parents, 0xb0, 0xb4, 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 24, 2, 31, 0x008, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* CLK_CFG_10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) aud_engen1_parents, 0xc0, 0xc4, 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 8, 2, 15, 0x008, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) aud_engen2_parents, 0xc0, 0xc4, 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 16, 2, 23, 0x008, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) faes_ufsfde_parents, 0xc0, 0xc4, 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 24, 3, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 0x008, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* CLK_CFG_11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x008, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 0xd0, 0xd4, 0xd8, 16, 1, 23, 0x008, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 0xd0, 0xd4, 0xd8, 24, 3, 31, 0x008, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* CLK_CFG_12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 0xe0, 0xe4, 0xe8, 0, 3, 7, 0x008, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 0xe0, 0xe4, 0xe8, 8, 4, 15, 0x008, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 0xe0, 0xe4, 0xe8, 16, 4, 23, 0x008, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 0xe0, 0xe4, 0xe8, 24, 2, 31, 0x004, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* CLK_CFG_13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x008, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) audio_h_parents, 0xf0, 0xf4, 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 8, 2, 15, 0x008, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 0xf0, 0xf4, 0xf8, 24, 3, 31, 0x008, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const char * const i2s0_m_ck_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "aud_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) "aud_2_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const char * const i2s1_m_ck_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) "aud_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "aud_2_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static const char * const i2s2_m_ck_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) "aud_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "aud_2_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const char * const i2s3_m_ck_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "aud_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "aud_2_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const char * const i2s4_m_ck_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "aud_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "aud_2_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const char * const i2s5_m_ck_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "aud_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) "aud_2_sel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const struct mtk_composite top_aud_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 0x320, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 0x320, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) 0x320, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 0x320, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 0x320, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 0x328, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static struct mtk_composite top_aud_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 0x320, 2, 0x324, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) 0x320, 3, 0x324, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 0x320, 4, 0x324, 8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) 0x320, 5, 0x324, 8, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 0x320, 6, 0x328, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 0x320, 7, 0x328, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 0x328, 16, 0x328, 4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const struct mtk_gate_regs infra0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .set_ofs = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .clr_ofs = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .sta_ofs = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const struct mtk_gate_regs infra1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .set_ofs = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .clr_ofs = 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .sta_ofs = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const struct mtk_gate_regs infra2_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .set_ofs = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .clr_ofs = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .sta_ofs = 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const struct mtk_gate_regs infra3_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .set_ofs = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .clr_ofs = 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .sta_ofs = 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define GATE_INFRA0(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) &mtk_clk_gate_ops_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define GATE_INFRA1(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) &mtk_clk_gate_ops_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define GATE_INFRA2(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) &mtk_clk_gate_ops_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define GATE_INFRA3(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) &mtk_clk_gate_ops_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static const struct mtk_gate infra_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* INFRA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "axi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) "axi_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "axi_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "axi_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "f_f26m_ck", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "axi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "axi_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) "axi_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "axi_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) "i2c_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "i2c_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "i2c_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) "i2c_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) "pwm_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "pwm_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "pwm_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) "pwm_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "pwm_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) "pwm_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) "uart_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) "uart_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "uart_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) "uart_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) "axi_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) "axi_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) "axi_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* INFRA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) "spi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) "msdc50_hclk_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) "axi_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) "axi_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) "msdc50_0_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) "f_f26m_ck", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) "axi_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) "axi_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) "f_f26m_ck", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) "axi_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) "axi_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) "axi_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) "f_f26m_ck", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) "msdc30_1_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) "msdc30_2_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) "axi_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) "axi_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) "axi_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) "axi_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) "axi_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) GATE_INFRA1(CLK_INFRA_AUD, "infra_audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) "axi_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) "axi_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) "dxcc_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) "dxcc_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) "axi_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) "f_f26m_ck", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* INFRA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) "f_f26m_ck", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) "usb_top_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) "axi_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) "infracfg_ao_audio_26m_bclk", "f_f26m_ck", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "spi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) "i2c_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) "f_f26m_ck", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "spi_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) "spi_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) "fufs_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) "fufs_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) "fufs_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) "axi_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) "axi_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "axi_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) "i2c_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) "i2c_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) "i2c_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) "i2c_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) "i2c_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) "i2c_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) "i2c_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "spi_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) "spi_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) "axi_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) "fufs_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) "faes_ufsfde_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) "fufs_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) "ssusb_top_xhci_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* INFRA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) "msdc50_0_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) "msdc50_0_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) "msdc50_0_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) "f_f26m_ck", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) "f_f26m_ck", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "axi_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) "i2c_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) "msdc50_hclk_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) "msdc50_hclk_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) "axi_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) "axi_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "axi_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) "axi_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) "f_f26m_ck", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "axi_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) "i2c_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) "i2c_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) "msdc50_0_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "dpmaif_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) "adsp_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "axi_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "axi_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) "spi_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "spi_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static const struct mtk_gate_regs apmixed_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .set_ofs = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .clr_ofs = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .sta_ofs = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define GATE_APMIXED(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * CRITICAL CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * apmixed_appll26m is the toppest clock gate of all PLLs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static const struct mtk_gate apmixed_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) "f_f26m_ck", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) "f_f26m_ck", 5, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) "f_f26m_ck", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) "f_f26m_ck", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) "f_f26m_ck", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) "f_f26m_ck", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) "f_f26m_ck", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) "f_f26m_ck", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) "f_f26m_ck", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) "f_f26m_ck", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) "f_f26m_ck", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define MT6779_PLL_FMAX (3800UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define MT6779_PLL_FMIN (1500UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) _pd_shift, _tuner_reg, _tuner_en_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) _tuner_en_bit, _pcw_reg, _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) _pcw_chg_reg, _div_table) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .pwr_reg = _pwr_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .en_mask = _en_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .rst_bar_mask = _rst_bar_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .fmax = MT6779_PLL_FMAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .fmin = MT6779_PLL_FMIN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .pcwbits = _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .pcwibits = _pcwibits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .pd_reg = _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .tuner_reg = _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .tuner_en_reg = _tuner_en_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .tuner_en_bit = _tuner_en_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .pcw_reg = _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .pcw_shift = _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .pcw_chg_reg = _pcw_chg_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .div_table = _div_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) _pd_shift, _tuner_reg, _tuner_en_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) _tuner_en_bit, _pcw_reg, _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) _pcw_chg_reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) _pd_shift, _tuner_reg, _tuner_en_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) _tuner_en_bit, _pcw_reg, _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) _pcw_chg_reg, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static const struct mtk_pll_data plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) 0x0234, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) 0, 0, 0, 0x0244, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) 0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) 0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) 0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) 0, 0, 0, 0x02b4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) 0, 0, 0, 0x0284, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) 0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) 0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) mtk_clk_register_gates(node, apmixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ARRAY_SIZE(apmixed_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static int clk_mt6779_top_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) node, &mt6779_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) base, &mt6779_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) base, &mt6779_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int clk_mt6779_infra_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const struct of_device_id of_match_clk_mt6779[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .compatible = "mediatek,mt6779-apmixed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .data = clk_mt6779_apmixed_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .compatible = "mediatek,mt6779-topckgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .data = clk_mt6779_top_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .compatible = "mediatek,mt6779-infracfg_ao",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .data = clk_mt6779_infra_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static int clk_mt6779_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) int (*clk_probe)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) clk_probe = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (!clk_probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) r = clk_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static struct platform_driver clk_mt6779_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .probe = clk_mt6779_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .name = "clk-mt6779",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .of_match_table = of_match_clk_mt6779,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int __init clk_mt6779_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return platform_driver_register(&clk_mt6779_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) arch_initcall(clk_mt6779_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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